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| author | Bo Shen <voice.shen@atmel.com> | 2014-12-15 13:24:36 +0800 |
|---|---|---|
| committer | Andreas Bießmann <andreas.devel@googlemail.com> | 2015-02-07 23:42:51 +0100 |
| commit | b54dd1b3adad4613bb8aa471b12f88bede699775 (patch) | |
| tree | f8222bd2d79101fdd3db4216df4b077185649241 /arch/arm | |
| parent | 569bbd3ceb1f3ca9d1f448178cd67f3eea4e01c4 (diff) | |
| download | u-boot-imx-b54dd1b3adad4613bb8aa471b12f88bede699775.zip u-boot-imx-b54dd1b3adad4613bb8aa471b12f88bede699775.tar.gz u-boot-imx-b54dd1b3adad4613bb8aa471b12f88bede699775.tar.bz2 | |
ARM: atmel: sama5d4: can access DDR in interleave mode
The SAMAA5D4 SoC can access DDR in interleave mode.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/at91-common/mpddrc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/at91-common/mpddrc.c b/arch/arm/cpu/at91-common/mpddrc.c index 44798e6..beec13d 100644 --- a/arch/arm/cpu/at91-common/mpddrc.c +++ b/arch/arm/cpu/at91-common/mpddrc.c @@ -19,7 +19,7 @@ static inline void atmel_mpddr_op(int mode, u32 ram_address) static int ddr2_decodtype_is_seq(u32 cr) { -#if defined(CONFIG_SAMA5D3) +#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED) return 0; #endif |