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| author | Hans de Goede <hdegoede@redhat.com> | 2015-01-25 12:10:48 +0100 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2015-02-02 13:55:14 +0100 |
| commit | c13f60d92a1c31c131a53ff8e994e4c8eebb8311 (patch) | |
| tree | 685c5822870b576ab2ccab53a02f572e8a4a873a /arch/arm | |
| parent | e1a0888ed224cc4c4e019a37b7b0331b11745e4d (diff) | |
| download | u-boot-imx-c13f60d92a1c31c131a53ff8e994e4c8eebb8311.zip u-boot-imx-c13f60d92a1c31c131a53ff8e994e4c8eebb8311.tar.gz u-boot-imx-c13f60d92a1c31c131a53ff8e994e4c8eebb8311.tar.bz2 | |
sunxi: Add a GMAC Transmit Clock Delay Chain Kconfig option
And use this to set the GMAC Transmit Clock Delay Chain value on Banana
boards, rather then keying of CONFIG_TARGET_FOO.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index 05fbad3..d297ed0 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -305,6 +305,8 @@ struct sunxi_ccm_reg { #define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2 #define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2) #define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2) +#define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5) +#define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10) #define CCM_USB_CTRL_PHY0_RST (0x1 << 0) #define CCM_USB_CTRL_PHY1_RST (0x1 << 1) diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index e101c54..8a80385 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -243,6 +243,8 @@ struct sunxi_ccm_reg { #define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2 #define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2) #define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2) +#define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5) +#define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10) #define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */ |