Merge git://git.denx.de/u-boot

68 files changed, 548 insertions, 7077 deletions

diff --git a/arch/arm/cpu/arm1176/tnetv107x/Makefile b/arch/arm/cpu/arm1176/tnetv107x/Makefile
index c63dc92..c1d4d67 100644
--- a/arch/arm/cpu/arm1176/tnetv107x/Makefile
+++ b/arch/arm/cpu/arm1176/tnetv107x/Makefile
@@ -21,7 +21,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).o
 
-COBJS	+= aemif.o clock.o init.o mux.o timer.o wdt.o
+COBJS	+= aemif.o clock.o init.o mux.o timer.o
 SOBJS	+= lowlevel_init.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/arm1176/tnetv107x/clock.c b/arch/arm/cpu/arm1176/tnetv107x/clock.c
index e26fec1..16876ae 100644
--- a/arch/arm/cpu/arm1176/tnetv107x/clock.c
+++ b/arch/arm/cpu/arm1176/tnetv107x/clock.c
@@ -168,10 +168,6 @@ static unsigned long pll_div_mask[] = { 0x01ff, 0x00ff, 0x00ff };
 #define tdm_extra_clk		{TDM_PLL, 1}
 #define tdm1_clk		{TDM_PLL, 2}
 
-/* Optimization barrier */
-#define barrier()	\
-	__asm__ __volatile__("mov r0, r0\n" : : : "memory");
-
 static const struct lpsc_map lpsc_clk_map[] = {
 	[TNETV107X_LPSC_ARM]			= sys_arm1176_clk,
 	[TNETV107X_LPSC_GEM]			= sys_dsp_clk,
diff --git a/arch/arm/cpu/arm1176/tnetv107x/wdt.c b/arch/arm/cpu/arm1176/tnetv107x/wdt.c
deleted file mode 100644
index 18aadb0..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/wdt.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * TNETV107X: Watchdog timer implementation (for reset)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-
-#define MAX_DIV		0xFFFE0001
-
-struct wdt_regs {
-	u32 kick_lock;
-#define KICK_LOCK_1	0x5555
-#define KICK_LOCK_2	0xaaaa
-	u32 kick;
-
-	u32 change_lock;
-#define CHANGE_LOCK_1	0x6666
-#define CHANGE_LOCK_2	0xbbbb
-	u32 change;
-
-	u32 disable_lock;
-#define DISABLE_LOCK_1	0x7777
-#define DISABLE_LOCK_2	0xcccc
-#define DISABLE_LOCK_3	0xdddd
-	u32 disable;
-
-	u32 prescale_lock;
-#define PRESCALE_LOCK_1	0x5a5a
-#define PRESCALE_LOCK_2	0xa5a5
-	u32 prescale;
-};
-
-static struct wdt_regs* regs = (struct wdt_regs *)TNETV107X_WDT0_ARM_BASE;
-
-#define wdt_reg_read(reg)	__raw_readl(&regs->reg)
-#define wdt_reg_write(reg, val)	__raw_writel((val), &regs->reg)
-
-static int write_prescale_reg(unsigned long prescale_value)
-{
-	wdt_reg_write(prescale_lock, PRESCALE_LOCK_1);
-	if ((wdt_reg_read(prescale_lock) & 0x3) != 0x1)
-		return -1;
-
-	wdt_reg_write(prescale_lock, PRESCALE_LOCK_2);
-	if ((wdt_reg_read(prescale_lock) & 0x3) != 0x3)
-		return -1;
-
-	wdt_reg_write(prescale, prescale_value);
-
-	return 0;
-}
-
-static int write_change_reg(unsigned long initial_timer_value)
-{
-	wdt_reg_write(change_lock, CHANGE_LOCK_1);
-	if ((wdt_reg_read(change_lock) & 0x3) != 0x1)
-		return -1;
-
-	wdt_reg_write(change_lock, CHANGE_LOCK_2);
-	if ((wdt_reg_read(change_lock) & 0x3) != 0x3)
-		return -1;
-
-	wdt_reg_write(change, initial_timer_value);
-
-	return 0;
-}
-
-static int wdt_control(unsigned long disable_value)
-{
-	wdt_reg_write(disable_lock, DISABLE_LOCK_1);
-	if ((wdt_reg_read(disable_lock) & 0x3) != 0x1)
-		return -1;
-
-	wdt_reg_write(disable_lock, DISABLE_LOCK_2);
-	if ((wdt_reg_read(disable_lock) & 0x3) != 0x2)
-		return -1;
-
-	wdt_reg_write(disable_lock, DISABLE_LOCK_3);
-	if ((wdt_reg_read(disable_lock) & 0x3) != 0x3)
-		return -1;
-
-	wdt_reg_write(disable, disable_value);
-	return 0;
-}
-
-static int wdt_set_period(unsigned long msec)
-{
-	unsigned long change_value, count_value;
-	unsigned long prescale_value = 1;
-	unsigned long refclk_khz, maxdiv;
-	int ret;
-
-	refclk_khz = clk_get_rate(TNETV107X_LPSC_WDT_ARM);
-	maxdiv = (MAX_DIV / refclk_khz);
-
-	if ((!msec) || (msec > maxdiv))
-		return -1;
-
-	count_value = refclk_khz * msec;
-	if (count_value > 0xffff) {
-		change_value = count_value / 0xffff + 1;
-		prescale_value = count_value / change_value;
-	} else {
-		change_value = count_value;
-	}
-
-	ret = write_prescale_reg(prescale_value - 1);
-	if (ret)
-		return ret;
-
-	ret = write_change_reg(change_value);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-unsigned long last_wdt = -1;
-
-int wdt_start(unsigned long msecs)
-{
-	int ret;
-	ret = wdt_control(0);
-	if (ret)
-		return ret;
-	ret = wdt_set_period(msecs);
-	if (ret)
-		return ret;
-	ret = wdt_control(1);
-	if (ret)
-		return ret;
-	ret = wdt_kick();
-	last_wdt = msecs;
-	return ret;
-}
-
-int wdt_stop(void)
-{
-	last_wdt = -1;
-	return wdt_control(0);
-}
-
-int wdt_kick(void)
-{
-	wdt_reg_write(kick_lock, KICK_LOCK_1);
-	if ((wdt_reg_read(kick_lock) & 0x3) != 0x1)
-		return -1;
-
-	wdt_reg_write(kick_lock, KICK_LOCK_2);
-	if ((wdt_reg_read(kick_lock) & 0x3) != 0x3)
-		return -1;
-
-	wdt_reg_write(kick, 1);
-	return 0;
-}
-
-void reset_cpu(ulong addr)
-{
-	clk_enable(TNETV107X_LPSC_WDT_ARM);
-	wdt_start(1);
-	wdt_kick();
-}
diff --git a/arch/arm/cpu/arm720t/cpu.c b/arch/arm/cpu/arm720t/cpu.c
index ce7b3c9..820614e 100644
--- a/arch/arm/cpu/arm720t/cpu.c
+++ b/arch/arm/cpu/arm720t/cpu.c
@@ -27,34 +27,12 @@
  */
 
 /*
- * CPU specific code
+ * cleanup_before_linux() - Prepare the CPU to jump to Linux
+ *
+ * This function is called just before we call Linux, it
+ * prepares the processor for linux
  */
-
-#include <common.h>
-#include <command.h>
-#include <clps7111.h>
-#include <asm/hardware.h>
-#include <asm/system.h>
-
-int cleanup_before_linux (void)
+int cleanup_before_linux(void)
 {
-	/*
-	 * this function is called just before we call linux
-	 * it prepares the processor for linux
-	 *
-	 * we turn off caches etc ...
-	 * and we set the CPU-speed to 73 MHz - see start.S for details
-	 */
-
-#if defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2292)
-	disable_interrupts ();
-	/* Nothing more needed */
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-	/* No cleanup before linux for IntegratorAP/CM720T as yet */
-#elif defined(CONFIG_TEGRA)
-	/* No cleanup before linux for tegra as yet */
-#else
-#error No cleanup_before_linux() defined for this CPU type
-#endif
 	return 0;
 }
diff --git a/arch/arm/cpu/arm720t/interrupts.c b/arch/arm/cpu/arm720t/interrupts.c
index c2f898f..623a24b 100644
--- a/arch/arm/cpu/arm720t/interrupts.c
+++ b/arch/arm/cpu/arm720t/interrupts.c
@@ -27,266 +27,23 @@
  */
 
 #include <common.h>
-#include <clps7111.h>
-#include <asm/proc-armv/ptrace.h>
-#include <asm/hardware.h>
-
-#ifndef CONFIG_NETARM
-/* we always count down the max. */
-#define TIMER_LOAD_VAL 0xffff
-/* macro to read the 16 bit timer */
-#define READ_TIMER (IO_TC1D & 0xffff)
-
-#ifdef CONFIG_LPC2292
-#undef READ_TIMER
-#define READ_TIMER (0xFFFFFFFF - GET32(T0TC))
-#endif
-
-#else
-#define IRQEN	(*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE))
-#define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL))
-#define TM2STAT (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_STATUS))
-#define TIMER_LOAD_VAL NETARM_GEN_TSTAT_CTC_MASK
-#define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK)
-#endif
-
-#ifdef CONFIG_S3C4510B
-/* require interrupts for the S3C4510B */
-# ifndef CONFIG_USE_IRQ
-#  error CONFIG_USE_IRQ _must_ be defined when using CONFIG_S3C4510B
-# else
-static struct _irq_handler IRQ_HANDLER[N_IRQS];
-# endif
-#endif	/* CONFIG_S3C4510B */
 
 #ifdef CONFIG_USE_IRQ
 void do_irq (struct pt_regs *pt_regs)
 {
-#if defined(CONFIG_S3C4510B)
-	unsigned int pending;
-
-	while ( (pending = GET_REG( REG_INTOFFSET)) != 0x54) {  /* sentinal value for no pending interrutps */
-		IRQ_HANDLER[pending>>2].m_func( IRQ_HANDLER[pending>>2].m_data);
-
-		/* clear pending interrupt */
-		PUT_REG( REG_INTPEND, (1<<(pending>>2)));
-	}
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-	/* No do_irq() for IntegratorAP/CM720T as yet */
-#elif defined(CONFIG_LPC2292)
-
-    void (*pfnct)(void);
-
-    pfnct = (void (*)(void))VICVectAddr;
-
-    (*pfnct)();
-#else
-#error do_irq() not defined for this CPU type
-#endif
-}
-#endif
-
-#ifdef CONFIG_S3C4510B
-static void default_isr( void *data) {
-	printf ("default_isr():  called for IRQ %d\n", (int)data);
-}
-
-static void timer_isr( void *data) {
-	unsigned int *pTime = (unsigned int *)data;
-
-	(*pTime)++;
-	if ( !(*pTime % (CONFIG_SYS_HZ/4))) {
-		/* toggle LED 0 */
-		PUT_REG( REG_IOPDATA, GET_REG(REG_IOPDATA) ^ 0x1);
-	}
-
 }
 #endif
 
-#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-	/* Use IntegratorAP routines in board/integratorap.c */
-#else
-
+#if defined(CONFIG_TEGRA)
 static ulong timestamp;
 static ulong lastdec;
 
-#if defined(CONFIG_USE_IRQ) && defined(CONFIG_S3C4510B)
-int arch_interrupt_init (void)
-{
-	int i;
-
-	/* install default interrupt handlers */
-	for ( i = 0; i < N_IRQS; i++) {
-		IRQ_HANDLER[i].m_data = (void *)i;
-		IRQ_HANDLER[i].m_func = default_isr;
-	}
-
-	/* configure interrupts for IRQ mode */
-	PUT_REG( REG_INTMODE, 0x0);
-	/* clear any pending interrupts */
-	PUT_REG( REG_INTPEND, 0x1FFFFF);
-
-	lastdec = 0;
-
-	/* install interrupt handler for timer */
-	IRQ_HANDLER[INT_TIMER0].m_data = (void *)&timestamp;
-	IRQ_HANDLER[INT_TIMER0].m_func = timer_isr;
-
-	return 0;
-}
-#endif
-
 int timer_init (void)
 {
-#if defined(CONFIG_NETARM)
-	/* disable all interrupts */
-	IRQEN = 0;
-
-	/* operate timer 2 in non-prescale mode */
-	TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CONFIG_SYS_HZ) |
-		    NETARM_GEN_TCTL_ENABLE |
-		    NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL));
-
-	/* set timer 2 counter */
-	lastdec = TIMER_LOAD_VAL;
-#elif defined(CONFIG_S3C4510B)
-	/* configure free running timer 0 */
-	PUT_REG( REG_TMOD, 0x0);
-	/* Stop timer 0 */
-	CLR_REG( REG_TMOD, TM0_RUN);
-
-	/* Configure for interval mode */
-	CLR_REG( REG_TMOD, TM1_TOGGLE);
-
-	/*
-	 * Load Timer data register with count down value.
-	 * count_down_val = CONFIG_SYS_SYS_CLK_FREQ/CONFIG_SYS_HZ
-	 */
-	PUT_REG( REG_TDATA0, (CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ));
-
-	/*
-	 * Enable global interrupt
-	 * Enable timer0 interrupt
-	 */
-	CLR_REG( REG_INTMASK, ((1<<INT_GLOBAL) | (1<<INT_TIMER0)));
-
-	/* Start timer */
-	SET_REG( REG_TMOD, TM0_RUN);
-#elif defined(CONFIG_LPC2292)
-	PUT32(T0IR, 0);		/* disable all timer0 interrupts */
-	PUT32(T0TCR, 0);	/* disable timer0 */
-	PUT32(T0PR, CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ);
-	PUT32(T0MCR, 0);
-	PUT32(T0TC, 0);
-	PUT32(T0TCR, 1);	/* enable timer0 */
-
-#elif defined(CONFIG_TEGRA)
 	/* No timer routines for tegra as yet */
 	lastdec = 0;
-#else
-#error No timer_init() defined for this CPU type
-#endif
 	timestamp = 0;
 
-	return (0);
-}
-
-#endif /* ! IntegratorAP */
-
-/*
- * timer without interrupts
- */
-
-
-#if defined(CONFIG_NETARM) || defined(CONFIG_LPC2292)
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void __udelay (unsigned long usec)
-{
-	ulong tmo;
-
-	tmo = usec / 1000;
-	tmo *= CONFIG_SYS_HZ;
-	tmo /= 1000;
-
-	tmo += get_timer (0);
-
-	while (get_timer_masked () < tmo)
-#ifdef CONFIG_LPC2292
-		/* GJ - not sure whether this is really needed or a misunderstanding */
-		__asm__ __volatile__(" nop");
-#else
-		/*NOP*/;
-#endif
-}
-
-ulong get_timer_masked (void)
-{
-	ulong now = READ_TIMER;
-
-	if (lastdec >= now) {
-		/* normal mode */
-		timestamp += lastdec - now;
-	} else {
-		/* we have an overflow ... */
-		timestamp += lastdec + TIMER_LOAD_VAL - now;
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-void udelay_masked (unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	if (usec >= 1000) {
-		tmo = usec / 1000;
-		tmo *= CONFIG_SYS_HZ;
-		tmo /= 1000;
-	} else {
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*1000);
-	}
-
-	endtime = get_timer_masked () + tmo;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-#elif defined(CONFIG_S3C4510B)
-
-ulong get_timer (ulong base)
-{
-	return timestamp - base;
-}
-
-void __udelay (unsigned long usec)
-{
-	u32 ticks;
-
-	ticks = (usec * CONFIG_SYS_HZ) / 1000000;
-
-	ticks += get_timer (0);
-
-	while (get_timer (0) < ticks)
-		/*NOP*/;
-
+	return 0;
 }
-
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-	/* No timer routines for IntegratorAP/CM720T as yet */
-#elif defined(CONFIG_TEGRA)
-	/* No timer routines for tegra as yet */
-#else
-#error Timer routines not defined for this CPU type
 #endif
diff --git a/arch/arm/cpu/arm720t/lpc2292/Makefile b/arch/arm/cpu/arm720t/lpc2292/Makefile
deleted file mode 100644
index 1b93008..0000000
--- a/arch/arm/cpu/arm720t/lpc2292/Makefile
+++ /dev/null
@@ -1,50 +0,0 @@
-#
-# (C) Copyright 2000-2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	= flash.o mmc.o mmc_hw.o spi.o
-SOBJS	= $(obj)iap_entry.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-# this MUST be compiled as thumb code!
-$(SOBJS):
-	$(CC) $(AFLAGS) -march=armv4t -c -o $(SOBJS) iap_entry.S
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm720t/lpc2292/flash.c b/arch/arm/cpu/arm720t/lpc2292/flash.c
deleted file mode 100644
index 3d2dc32..0000000
--- a/arch/arm/cpu/arm720t/lpc2292/flash.c
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
- *
- * Modified to remove all but the IAP-command related code by
- * Gary Jennejohn <garyj@denx.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-/* IAP commands use 32 bytes at the top of CPU internal sram, we
-   use 512 bytes below that */
-#define COPY_BUFFER_LOCATION 0x40003de0
-
-#define IAP_LOCATION 0x7ffffff1
-#define IAP_CMD_PREPARE 50
-#define IAP_CMD_COPY 51
-#define IAP_CMD_ERASE 52
-#define IAP_CMD_CHECK 53
-#define IAP_CMD_ID 54
-#define IAP_CMD_VERSION 55
-#define IAP_CMD_COMPARE 56
-
-#define IAP_RET_CMD_SUCCESS 0
-
-static unsigned long command[5];
-static unsigned long result[2];
-
-extern void iap_entry(unsigned long * command, unsigned long * result);
-
-/*-----------------------------------------------------------------------
- *
- */
-static int get_flash_sector(flash_info_t * info, ulong flash_addr)
-{
-	int i;
-
-	for(i = 1; i < (info->sector_count); i++) {
-		if (flash_addr < (info->start[i]))
-			break;
-	}
-
-	return (i-1);
-}
-
-/*-----------------------------------------------------------------------
- * This function assumes that flash_addr is aligned on 512 bytes boundary
- * in flash. This function also assumes that prepare have been called
- * for the sector in question.
- */
-int lpc2292_copy_buffer_to_flash(flash_info_t * info, ulong flash_addr)
-{
-	int first_sector;
-	int last_sector;
-
-	first_sector = get_flash_sector(info, flash_addr);
-	last_sector = get_flash_sector(info, flash_addr + 512 - 1);
-
-	/* prepare sectors for write */
-	command[0] = IAP_CMD_PREPARE;
-	command[1] = first_sector;
-	command[2] = last_sector;
-	iap_entry(command, result);
-	if (result[0] != IAP_RET_CMD_SUCCESS) {
-		printf("IAP prepare failed\n");
-		return ERR_PROG_ERROR;
-	}
-
-	command[0] = IAP_CMD_COPY;
-	command[1] = flash_addr;
-	command[2] = COPY_BUFFER_LOCATION;
-	command[3] = 512;
-	command[4] = CONFIG_SYS_SYS_CLK_FREQ >> 10;
-	iap_entry(command, result);
-	if (result[0] != IAP_RET_CMD_SUCCESS) {
-		printf("IAP copy failed\n");
-		return 1;
-	}
-
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int lpc2292_flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	int flag;
-	int prot;
-	int sect;
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-	if (prot)
-		return ERR_PROTECTED;
-
-
-	flag = disable_interrupts();
-
-	printf ("Erasing %d sectors starting at sector %2d.\n"
-	"This make take some time ... ",
-	s_last - s_first + 1, s_first);
-
-	command[0] = IAP_CMD_PREPARE;
-	command[1] = s_first;
-	command[2] = s_last;
-	iap_entry(command, result);
-	if (result[0] != IAP_RET_CMD_SUCCESS) {
-		printf("IAP prepare failed\n");
-		return ERR_PROTECTED;
-	}
-
-	command[0] = IAP_CMD_ERASE;
-	command[1] = s_first;
-	command[2] = s_last;
-	command[3] = CONFIG_SYS_SYS_CLK_FREQ >> 10;
-	iap_entry(command, result);
-	if (result[0] != IAP_RET_CMD_SUCCESS) {
-		printf("IAP erase failed\n");
-		return ERR_PROTECTED;
-	}
-
-	if (flag)
-		enable_interrupts();
-
-	return ERR_OK;
-}
-
-int lpc2292_write_buff (flash_info_t * info, uchar * src, ulong addr,
-			ulong cnt)
-{
-	int first_copy_size;
-	int last_copy_size;
-	int first_block;
-	int last_block;
-	int nbr_mid_blocks;
-	uchar memmap_value;
-	ulong i;
-	uchar* src_org;
-	uchar* dst_org;
-	int ret = ERR_OK;
-
-	src_org = src;
-	dst_org = (uchar*)addr;
-
-	first_block = addr / 512;
-	last_block = (addr + cnt) / 512;
-	nbr_mid_blocks = last_block - first_block - 1;
-
-	first_copy_size = 512 - (addr % 512);
-	last_copy_size = (addr + cnt) % 512;
-
-	debug("\ncopy first block: (1) %lX -> %lX 0x200 bytes, "
-		"(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX 0x200 bytes\n",
-	(ulong)(first_block * 512),
-	(ulong)COPY_BUFFER_LOCATION,
-	(ulong)src,
-	(ulong)(COPY_BUFFER_LOCATION + 512 - first_copy_size),
-	first_copy_size,
-	(ulong)COPY_BUFFER_LOCATION,
-	(ulong)(first_block * 512));
-
-	/* copy first block */
-	memcpy((void*)COPY_BUFFER_LOCATION,
-		(void*)(first_block * 512), 512);
-	memcpy((void*)(COPY_BUFFER_LOCATION + 512 - first_copy_size),
-		src, first_copy_size);
-	lpc2292_copy_buffer_to_flash(info, first_block * 512);
-	src += first_copy_size;
-	addr += first_copy_size;
-
-	/* copy middle blocks */
-	for (i = 0; i < nbr_mid_blocks; i++) {
-		debug("copy middle block: %lX -> %lX 512 bytes, "
-		"%lX -> %lX 512 bytes\n",
-		(ulong)src,
-		(ulong)COPY_BUFFER_LOCATION,
-		(ulong)COPY_BUFFER_LOCATION,
-		(ulong)addr);
-
-		memcpy((void*)COPY_BUFFER_LOCATION, src, 512);
-		lpc2292_copy_buffer_to_flash(info, addr);
-		src += 512;
-		addr += 512;
-	}
-
-
-	if (last_copy_size > 0) {
-		debug("copy last block: (1) %lX -> %lX 0x200 bytes, "
-		"(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX x200 bytes\n",
-		(ulong)(last_block * 512),
-		(ulong)COPY_BUFFER_LOCATION,
-		(ulong)src,
-		(ulong)(COPY_BUFFER_LOCATION),
-		last_copy_size,
-		(ulong)COPY_BUFFER_LOCATION,
-		(ulong)addr);
-
-		/* copy last block */
-		memcpy((void*)COPY_BUFFER_LOCATION,
-			(void*)(last_block * 512), 512);
-		memcpy((void*)COPY_BUFFER_LOCATION,
-			src, last_copy_size);
-		lpc2292_copy_buffer_to_flash(info, addr);
-	}
-
-	/* verify write */
-	memmap_value = GET8(MEMMAP);
-
-	disable_interrupts();
-
-	PUT8(MEMMAP, 01);		/* we must make sure that initial 64
-							   bytes are taken from flash when we
-							   do the compare */
-
-	for (i = 0; i < cnt; i++) {
-		if (*dst_org != *src_org){
-			printf("Write failed. Byte %lX differs\n", i);
-			ret = ERR_PROG_ERROR;
-			break;
-		}
-		dst_org++;
-		src_org++;
-	}
-
-	PUT8(MEMMAP, memmap_value);
-	enable_interrupts();
-
-	return ret;
-}
diff --git a/arch/arm/cpu/arm720t/lpc2292/iap_entry.S b/arch/arm/cpu/arm720t/lpc2292/iap_entry.S
deleted file mode 100644
index c31d519..0000000
--- a/arch/arm/cpu/arm720t/lpc2292/iap_entry.S
+++ /dev/null
@@ -1,7 +0,0 @@
-IAP_ADDRESS:	.word	0x7FFFFFF1
-
-.globl iap_entry
-iap_entry:
-	ldr	r2, IAP_ADDRESS
-	bx	r2
-	mov	pc, lr
diff --git a/arch/arm/cpu/arm720t/lpc2292/mmc.c b/arch/arm/cpu/arm720t/lpc2292/mmc.c
deleted file mode 100644
index beaffe9..0000000
--- a/arch/arm/cpu/arm720t/lpc2292/mmc.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <common.h>
-#include <mmc.h>
-#include <asm/errno.h>
-#include <asm/arch/hardware.h>
-#include <part.h>
-#include <fat.h>
-#include "mmc_hw.h"
-#include <asm/arch/spi.h>
-
-#ifdef CONFIG_MMC
-
-#undef MMC_DEBUG
-
-static block_dev_desc_t mmc_dev;
-
-/* these are filled out by a call to mmc_hw_get_parameters */
-static int hw_size;		/* in kbytes */
-static int hw_nr_sects;
-static int hw_sect_size;	/* in bytes */
-
-block_dev_desc_t * mmc_get_dev(int dev)
-{
-	return (block_dev_desc_t *)(&mmc_dev);
-}
-
-unsigned long mmc_block_read(int dev,
-			     unsigned long start,
-			     lbaint_t blkcnt,
-			     void *buffer)
-{
-	unsigned long rc = 0;
-	unsigned char *p = (unsigned char *)buffer;
-	unsigned long i;
-	unsigned long addr = start;
-
-#ifdef MMC_DEBUG
-	printf("mmc_block_read: start=%lu, blkcnt=%lu\n", start,
-		 (unsigned long)blkcnt);
-#endif
-
-	for(i = 0; i < (unsigned long)blkcnt; i++) {
-#ifdef MMC_DEBUG
-		printf("mmc_read_sector: addr=%lu, buffer=%p\n", addr, p);
-#endif
-		(void)mmc_read_sector(addr, p);
-		rc++;
-		addr++;
-		p += hw_sect_size;
-	}
-
-	return rc;
-}
-
-/*-----------------------------------------------------------------------------
- * Read hardware paramterers (sector size, size, number of sectors)
- */
-static int mmc_hw_get_parameters(void)
-{
-	unsigned char csddata[16];
-	unsigned int sizemult;
-	unsigned int size;
-
-	mmc_read_csd(csddata);
-	hw_sect_size = 1<<(csddata[5] & 0x0f);
-	size = ((csddata[6]&0x03)<<10)+(csddata[7]<<2)+(csddata[8]&0xc0);
-	sizemult = ((csddata[10] & 0x80)>>7)+((csddata[9] & 0x03)<<1);
-	hw_nr_sects = (size+1)*(1<<(sizemult+2));
-	hw_size = hw_nr_sects*hw_sect_size/1024;
-
-#ifdef MMC_DEBUG
-	printf("mmc_hw_get_parameters: hw_sect_size=%d, hw_nr_sects=%d, "
-		 "hw_size=%d\n", hw_sect_size, hw_nr_sects, hw_size);
-#endif
-
-	return 0;
-}
-
-int mmc_legacy_init(int verbose)
-{
-	int ret = -ENODEV;
-
-	if (verbose)
-		printf("mmc_legacy_init\n");
-
-	spi_init();
-	/* this meeds to be done twice */
-	mmc_hw_init();
-	udelay(1000);
-	mmc_hw_init();
-
-	mmc_hw_get_parameters();
-
-	mmc_dev.if_type = IF_TYPE_MMC;
-	mmc_dev.part_type = PART_TYPE_DOS;
-	mmc_dev.dev = 0;
-	mmc_dev.lun = 0;
-	mmc_dev.type = 0;
-	mmc_dev.blksz = hw_sect_size;
-	mmc_dev.lba = hw_nr_sects;
-	sprintf((char*)mmc_dev.vendor, "Unknown vendor");
-	sprintf((char*)mmc_dev.product, "Unknown product");
-	sprintf((char*)mmc_dev.revision, "N/A");
-	mmc_dev.removable = 0;	/* should be true??? */
-	mmc_dev.block_read = mmc_block_read;
-
-	fat_register_device(&mmc_dev, 1);
-
-	ret = 0;
-
-	return ret;
-}
-
-#endif /* CONFIG_MMC */
diff --git a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c b/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c
deleted file mode 100644
index bd6a5b1..0000000
--- a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c
+++ /dev/null
@@ -1,233 +0,0 @@
-/*
-    This code was original written by Ulrich Radig and modified by
-    Embedded Artists AB (www.embeddedartists.com).
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#include <config.h>
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spi.h>
-
-#define MMC_Enable() PUT32(IO1CLR, 1l << 22)
-#define MMC_Disable() PUT32(IO1SET, 1l << 22)
-#define mmc_spi_cfg() spi_set_clock(8); spi_set_cfg(0, 1, 0);
-
-static unsigned char Write_Command_MMC (unsigned char *CMD);
-static void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer,
-		    unsigned short int Bytes);
-
-/* initialize the hardware */
-int mmc_hw_init(void)
-{
-	unsigned long a;
-	unsigned short int Timeout = 0;
-	unsigned char b;
-	unsigned char CMD[] = {0x40, 0x00, 0x00, 0x00, 0x00, 0x95};
-
-	/* set-up GPIO and SPI */
-	(*((volatile unsigned long *)PINSEL2)) &= ~(1l << 3); /* clear bit 3 */
-	(*((volatile unsigned long *)IO1DIR)) |= (1l << 22); /* set bit 22 (output) */
-
-	MMC_Disable();
-
-	spi_lock();
-	spi_set_clock(248);
-	spi_set_cfg(0, 1, 0);
-	MMC_Enable();
-
-	/* waste some time */
-	for(a=0; a < 20000; a++)
-		asm("nop");
-
-	/* Put the MMC/SD-card into SPI-mode */
-	for (b = 0; b < 10; b++) /* Sends min 74+ clocks to the MMC/SD-card */
-		spi_write(0xff);
-
-	/* Sends command CMD0 to MMC/SD-card */
-	while (Write_Command_MMC(CMD) != 1) {
-		if (Timeout++ > 200) {
-			MMC_Disable();
-			spi_unlock();
-			return(1); /* Abort with command 1 (return 1) */
-		}
-	}
-	/* Sends Command CMD1 an MMC/SD-card */
-	Timeout = 0;
-	CMD[0] = 0x41;/* Command 1 */
-	CMD[5] = 0xFF;
-
-	while (Write_Command_MMC(CMD) != 0) {
-		if (Timeout++ > 200) {
-			MMC_Disable();
-			spi_unlock();
-			return (2); /* Abort with command 2 (return 2) */
-		}
-	}
-
-	MMC_Disable();
-	spi_unlock();
-
-	return 0;
-}
-
-/* ############################################################################
-   Sends a command to the MMC/SD-card
-   ######################################################################### */
-static unsigned char Write_Command_MMC (unsigned char *CMD)
-{
-	unsigned char a, tmp = 0xff;
-	unsigned short int Timeout = 0;
-
-	MMC_Disable();
-	spi_write(0xFF);
-	MMC_Enable();
-
-	for (a = 0; a < 0x06; a++)
-		spi_write(*CMD++);
-
-	while (tmp == 0xff) {
-		tmp = spi_read();
-		if (Timeout++ > 5000)
-		  break;
-	}
-
-	return (tmp);
-}
-
-/* ############################################################################
-   Routine to read the CID register from the MMC/SD-card (16 bytes)
-   ######################################################################### */
-void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer, unsigned short
-	int Bytes)
-{
-	unsigned short int a;
-
-	spi_lock();
-	mmc_spi_cfg();
-	MMC_Enable();
-
-	if (Write_Command_MMC(CMD) != 0) {
-		MMC_Disable();
-		spi_unlock();
-		return;
-	}
-
-	while (spi_read() != 0xfe) {};
-	for (a = 0; a < Bytes; a++)
-		*Buffer++ = spi_read();
-
-	/* Read the CRC-byte */
-	spi_read(); /* CRC - byte is discarded */
-	spi_read(); /* CRC - byte is discarded */
-	/* set MMC_Chip_Select to high (MMC/SD-card Inaktiv) */
-	MMC_Disable();
-	spi_unlock();
-
-	return;
-}
-
-/* ############################################################################
-   Routine to read a block (512 bytes) from the MMC/SD-card
-   ######################################################################### */
-unsigned char mmc_read_sector (unsigned long addr,unsigned char *Buffer)
-{
-	/* Command 16 to read aBlocks from the MMC/SD - caed */
-	unsigned char CMD[] = {0x51,0x00,0x00,0x00,0x00,0xFF};
-
-	/* The address on the MMC/SD-card is in bytes,
-	addr is transformed from blocks to bytes and the result is
-	placed into the command */
-
-	addr = addr << 9; /* addr = addr * 512 */
-
-	CMD[1] = ((addr & 0xFF000000) >> 24);
-	CMD[2] = ((addr & 0x00FF0000) >> 16);
-	CMD[3] = ((addr & 0x0000FF00) >> 8 );
-
-	MMC_Read_Block(CMD, Buffer, 512);
-
-	return (0);
-}
-
-/* ############################################################################
-   Routine to write a block (512 byte) to the MMC/SD-card
-   ######################################################################### */
-unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer)
-{
-	unsigned char tmp, a;
-	unsigned short int b;
-	/* Command 24 to write a block to the MMC/SD - card */
-	unsigned char CMD[] = {0x58, 0x00, 0x00, 0x00, 0x00, 0xFF};
-
-	/* The address on the MMC/SD-card is in bytes,
-	addr is transformed from blocks to bytes and the result is
-	placed into the command */
-
-	addr = addr << 9; /* addr = addr * 512 */
-
-	CMD[1] = ((addr & 0xFF000000) >> 24);
-	CMD[2] = ((addr & 0x00FF0000) >> 16);
-	CMD[3] = ((addr & 0x0000FF00) >> 8 );
-
-	spi_lock();
-	mmc_spi_cfg();
-	MMC_Enable();
-
-	/* Send command CMD24 to the MMC/SD-card (Write 1 Block/512 Bytes) */
-	tmp = Write_Command_MMC(CMD);
-	if (tmp != 0) {
-		MMC_Disable();
-		spi_unlock();
-		return(tmp);
-	}
-
-	/* Do a short delay and send a clock-pulse to the MMC/SD-card */
-	for (a = 0; a < 100; a++)
-		spi_read();
-
-	/* Send a start byte to the MMC/SD-card */
-	spi_write(0xFE);
-
-	/* Write the block (512 bytes) to the MMC/SD-card */
-	for (b = 0; b < 512; b++)
-		spi_write(*Buffer++);
-
-	/* write the CRC-Byte */
-	spi_write(0xFF); /* write a dummy CRC */
-	spi_write(0xFF); /* CRC code is not used */
-
-	/* Wait for MMC/SD-card busy */
-	while (spi_read() != 0xff) {};
-
-	/* set MMC_Chip_Select to high (MMC/SD-card inactive) */
-	MMC_Disable();
-	spi_unlock();
-	return (0);
-}
-
-/* #########################################################################
-   Routine to read the CSD register from the MMC/SD-card (16 bytes)
-   ######################################################################### */
-unsigned char mmc_read_csd (unsigned char *Buffer)
-{
-	/* Command to read the CSD register */
-	unsigned char CMD[] = {0x49, 0x00, 0x00, 0x00, 0x00, 0xFF};
-
-	MMC_Read_Block(CMD, Buffer, 16);
-
-	return (0);
-}
diff --git a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.h b/arch/arm/cpu/arm720t/lpc2292/mmc_hw.h
deleted file mode 100644
index 3687dbf..0000000
--- a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
-    This module implements a linux character device driver for the 24c256 chip.
-    Copyright (C) 2006  Embedded Artists AB (www.embeddedartists.com)
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#ifndef _MMC_HW_
-#define _MMC_HW_
-
-unsigned char mmc_read_csd(unsigned char *Buffer);
-unsigned char mmc_read_sector (unsigned long addr,
-			       unsigned char *Buffer);
-unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer);
-int mmc_hw_init(void);
-
-#endif /* _MMC_HW_ */
diff --git a/arch/arm/cpu/arm720t/lpc2292/spi.c b/arch/arm/cpu/arm720t/lpc2292/spi.c
deleted file mode 100644
index d296bda..0000000
--- a/arch/arm/cpu/arm720t/lpc2292/spi.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
-    This module implements an interface to the SPI on the lpc22xx.
-    Copyright (C) 2006  Embedded Artists AB (www.embeddedartists.com)
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#include <config.h>
-#include <common.h>
-#include <asm/errno.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spi.h>
-
-unsigned long spi_flags;
-unsigned char spi_idle = 0x00;
-
-int spi_init(void)
-{
-	unsigned long pinsel0_value;
-
-	/* activate spi pins */
-	pinsel0_value = GET32(PINSEL0);
-	pinsel0_value &= ~(0xFFl << 8);
-	pinsel0_value |= (0x55l << 8);
-	PUT32(PINSEL0, pinsel0_value);
-
-	return 0;
-}
diff --git a/arch/arm/cpu/arm720t/s3c4510b/Makefile b/arch/arm/cpu/arm720t/s3c4510b/Makefile
deleted file mode 100644
index 5c6df08..0000000
--- a/arch/arm/cpu/arm720t/s3c4510b/Makefile
+++ /dev/null
@@ -1,45 +0,0 @@
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y	+= cache.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm720t/s3c4510b/cache.c b/arch/arm/cpu/arm720t/s3c4510b/cache.c
deleted file mode 100644
index 104d287..0000000
--- a/arch/arm/cpu/arm720t/s3c4510b/cache.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/hardware.h>
-
-void icache_enable (void)
-{
-	s32 i;
-
-	/* disable all cache bits */
-	CLR_REG( REG_SYSCFG, 0x3F);
-
-	/* 8KB cache, write enable */
-	SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01);
-
-	/* clear TAG RAM bits */
-	for ( i = 0; i < 256; i++)
-	  PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000);
-
-	/* clear SET0 RAM */
-	for(i=0; i < 1024; i++)
-	  PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000);
-
-	/* clear SET1 RAM */
-	for(i=0; i < 1024; i++)
-	  PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000);
-
-	/* enable cache */
-	SET_REG( REG_SYSCFG, CACHE_ENABLE);
-
-}
-
-void icache_disable (void)
-{
-	/* disable all cache bits */
-	CLR_REG( REG_SYSCFG, 0x3F);
-}
-
-int icache_status (void)
-{
-	return GET_REG( REG_SYSCFG) & CACHE_ENABLE;
-}
-
-void dcache_enable (void)
-{
-	/* we don't have seperate instruction/data caches */
-	icache_enable();
-}
-
-void dcache_disable (void)
-{
-	/* we don't have seperate instruction/data caches */
-	icache_disable();
-}
-
-int dcache_status (void)
-{
-	/* we don't have seperate instruction/data caches */
-	return icache_status();
-}
diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S
index 2f914e9..c2a7763 100644
--- a/arch/arm/cpu/arm720t/start.S
+++ b/arch/arm/cpu/arm720t/start.S
@@ -43,11 +43,7 @@ _start: b	reset
 	ldr	pc, _software_interrupt
 	ldr	pc, _prefetch_abort
 	ldr	pc, _data_abort
-#ifdef CONFIG_LPC2292
-	.word	0xB4405F76 /* 2's complement of the checksum of the vectors */
-#else
 	ldr	pc, _not_used
-#endif
 	ldr	pc, _irq
 	ldr	pc, _fiq
 
@@ -151,10 +147,6 @@ reset:
 	bl	cpu_init_crit
 #endif
 
-#ifdef CONFIG_LPC2292
-	bl	lowlevel_init
-#endif
-
 /* Set stackpointer in internal RAM to call board_init_f */
 call_board_init_f:
 	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
@@ -291,148 +283,9 @@ _dynsym_start_ofs:
  *************************************************************************
  */
 
-#if defined(CONFIG_LPC2292)
-PLLCFG_ADR:	.word	PLLCFG
-PLLFEED_ADR:	.word	PLLFEED
-PLLCON_ADR:	.word	PLLCON
-PLLSTAT_ADR:	.word	PLLSTAT
-VPBDIV_ADR:	.word	VPBDIV
-MEMMAP_ADR:	.word	MEMMAP
-
-#endif
-
 cpu_init_crit:
-#if defined(CONFIG_NETARM)
-	/*
-	 * prior to software reset : need to set pin PORTC4 to be *HRESET
-	 */
-	ldr	r0, =NETARM_GEN_MODULE_BASE
-	ldr	r1, =(NETARM_GEN_PORT_MODE(0x10) | \
-			NETARM_GEN_PORT_DIR(0x10))
-	str	r1, [r0, #+NETARM_GEN_PORTC]
-	/*
-	 * software reset : see HW Ref. Guide 8.2.4 : Software Service register
-	 *		    for an explanation of this process
-	 */
-	ldr	r0, =NETARM_GEN_MODULE_BASE
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
-	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
-	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
-	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
-	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
-	/*
-	 * setup PLL and System Config
-	 */
-	ldr	r0, =NETARM_GEN_MODULE_BASE
-
-	ldr	r1, =(	NETARM_GEN_SYS_CFG_LENDIAN | \
-			NETARM_GEN_SYS_CFG_BUSFULL | \
-			NETARM_GEN_SYS_CFG_USER_EN | \
-			NETARM_GEN_SYS_CFG_ALIGN_ABORT | \
-			NETARM_GEN_SYS_CFG_BUSARB_INT | \
-			NETARM_GEN_SYS_CFG_BUSMON_EN )
-
-	str	r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL]
-
-#ifndef CONFIG_NETARM_PLL_BYPASS
-	ldr	r1, =(	NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \
-			NETARM_GEN_PLL_CTL_POLTST_DEF | \
-			NETARM_GEN_PLL_CTL_INDIV(1) | \
-			NETARM_GEN_PLL_CTL_ICP_DEF | \
-			NETARM_GEN_PLL_CTL_OUTDIV(2) )
-	str	r1, [r0, #+NETARM_GEN_PLL_CONTROL]
-#endif
-
-	/*
-	 * mask all IRQs by clearing all bits in the INTMRs
-	 */
-	mov	r1, #0
-	ldr	r0, =NETARM_GEN_MODULE_BASE
-	str	r1, [r0, #+NETARM_GEN_INTR_ENABLE]
-
-#elif defined(CONFIG_S3C4510B)
 
-	/*
-	 * Mask off all IRQ sources
-	 */
-	ldr	r1, =REG_INTMASK
-	ldr	r0, =0x3FFFFF
-	str	r0, [r1]
-
-	/*
-	 * Disable Cache
-	 */
-	ldr r0, =REG_SYSCFG
-	ldr r1, =0x83ffffa0	/* cache-disabled  */
-	str r1, [r0]
-
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-	/* No specific initialisation for IntegratorAP/CM720T as yet */
-#elif defined(CONFIG_LPC2292)
-	/* Set-up PLL */
-	mov	r3, #0xAA
-	mov	r4, #0x55
-	/* First disconnect and disable the PLL */
-	ldr	r0, PLLCON_ADR
-	mov	r1, #0x00
-	str	r1, [r0]
-	ldr	r0, PLLFEED_ADR /* start feed sequence */
-	str	r3, [r0]
-	str	r4, [r0]	/* feed sequence done */
-	/* Set new M and P values */
-	ldr	r0, PLLCFG_ADR
-	mov	r1, #0x23	/* M=4 and P=2 */
-	str	r1, [r0]
-	ldr	r0, PLLFEED_ADR /* start feed sequence */
-	str	r3, [r0]
-	str	r4, [r0]	/* feed sequence done */
-	/* Then enable the PLL */
-	ldr	r0, PLLCON_ADR
-	mov	r1, #0x01	/* PLL enable bit */
-	str	r1, [r0]
-	ldr	r0, PLLFEED_ADR /* start feed sequence */
-	str	r3, [r0]
-	str	r4, [r0]	/* feed sequence done */
-	/* Wait for the lock */
-	ldr	r0, PLLSTAT_ADR
-	mov	r1, #0x400	/* lock bit */
-lock_loop:
-	ldr	r2, [r0]
-	and	r2, r1, r2
-	cmp	r2, #0
-	beq	lock_loop
-	/* And finally connect the PLL */
-	ldr	r0, PLLCON_ADR
-	mov	r1, #0x03	/* PLL enable bit and connect bit */
-	str	r1, [r0]
-	ldr	r0, PLLFEED_ADR /* start feed sequence */
-	str	r3, [r0]
-	str	r4, [r0]	/* feed sequence done */
-	/* Set-up VPBDIV register */
-	ldr	r0, VPBDIV_ADR
-	mov	r1, #0x01	/* VPB clock is same as process clock */
-	str	r1, [r0]
-#elif defined(CONFIG_TEGRA)
-	/* No cpu_init_crit for tegra as yet */
-#else
-#error No cpu_init_crit() defined for current CPU type
-#endif
-
-#ifdef CONFIG_ARM7_REVD
-	/* set clock speed */
-	/* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
-	/* !!! not doing DRAM refresh properly! */
-	ldr	r0, SYSCON3
-	ldr	r1, [r0]
-	bic	r1, r1, #CLKCTL
-	orr	r1, r1, #CLKCTL_36
-	str	r1, [r0]
-#endif
-
-#if !defined(CONFIG_LPC2292) && !defined(CONFIG_TEGRA)
+#if !defined(CONFIG_TEGRA)
 	mov	ip, lr
 	/*
 	 * before relocating, we have to setup RAM timing
@@ -610,39 +463,3 @@ fiq:
 
 #endif
 #endif /* CONFIG_SPL_BUILD */
-
-#if defined(CONFIG_NETARM)
-	.align	5
-.globl reset_cpu
-reset_cpu:
-	ldr	r1, =NETARM_MEM_MODULE_BASE
-	ldr	r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR]
-	ldr	r1, =0xFFFFF000
-	and	r0, r1, r0
-	ldr	r1, =(relocate-CONFIG_SYS_TEXT_BASE)
-	add	r0, r1, r0
-	ldr	r4, =NETARM_GEN_MODULE_BASE
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
-	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
-	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
-	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
-	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
-	mov	pc, r0
-#elif defined(CONFIG_S3C4510B)
-/* Nothing done here as reseting the CPU is board specific, depending
- * on external peripherals such as watchdog timers, etc. */
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-	/* No specific reset actions for IntegratorAP/CM720T as yet */
-#elif defined(CONFIG_LPC2292)
-	.align	5
-.globl reset_cpu
-reset_cpu:
-	mov	pc, r0
-#elif defined(CONFIG_TEGRA)
-	/* No specific reset actions for tegra as yet */
-#else
-#error No reset_cpu() defined for current CPU type
-#endif
diff --git a/arch/arm/cpu/arm720t/tegra-common/spl.c b/arch/arm/cpu/arm720t/tegra-common/spl.c
index 0d37ce8..c280ab7 100644
--- a/arch/arm/cpu/arm720t/tegra-common/spl.c
+++ b/arch/arm/cpu/arm720t/tegra-common/spl.c
@@ -23,105 +23,42 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
-#include <asm/u-boot.h>
-#include <asm/utils.h>
-#include <nand.h>
-#include <mmc.h>
-#include <fat.h>
-#include <version.h>
-#include <i2c.h>
-#include <image.h>
-#include <malloc.h>
-#include <linux/compiler.h>
 #include "cpu.h"
+#include <spl.h>
 
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/tegra.h>
 #include <asm/arch-tegra/board.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/pmc.h>
-#include <asm/arch-tegra/scu.h>
-#include <asm/arch-tegra/sys_proto.h>
+#include <asm/arch/spl.h>
 
-DECLARE_GLOBAL_DATA_PTR;
 
-/* Define global data structure pointer to it*/
-static gd_t gdata __attribute__ ((section(".data")));
-static bd_t bdata __attribute__ ((section(".data")));
-
-inline void hang(void)
+void spl_board_init(void)
 {
-	puts("### ERROR ### Please RESET the board ###\n");
-	for (;;)
-		;
-}
+	struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+
+	/* enable JTAG */
+	writel(0xC0, &pmt->pmt_cfg_ctl);
 
-void board_init_f(ulong dummy)
-{
 	board_init_uart_f();
 
 	/* Initialize periph GPIOs */
 	gpio_early_init_uart();
 
-	/*
-	 * We call relocate_code() with relocation target same as the
-	 * CONFIG_SYS_SPL_TEXT_BASE. This will result in relocation getting
-	 * skipped. Instead, only .bss initialization will happen. That's
-	 * all we need
-	 */
-	debug(">>board_init_f()\n");
-	relocate_code(CONFIG_SPL_STACK, &gdata, CONFIG_SPL_TEXT_BASE);
+	clock_early_init();
+	preloader_console_init();
 }
 
-/* This requires UART clocks to be enabled */
-static void preloader_console_init(void)
+u32 spl_boot_device(void)
 {
-	const char *u_boot_rev = U_BOOT_VERSION;
-
-	gd = &gdata;
-	gd->bd = &bdata;
-	gd->flags |= GD_FLG_RELOC;
-	gd->baudrate = CONFIG_BAUDRATE;
-
-	serial_init();		/* serial communications setup */
-
-	gd->have_console = 1;
-
-	/* Avoid a second "U-Boot" coming from this string */
-	u_boot_rev = &u_boot_rev[7];
-
-	printf("\nU-Boot SPL %s (%s - %s)\n", u_boot_rev, U_BOOT_DATE,
-		U_BOOT_TIME);
+	return BOOT_DEVICE_RAM;
 }
 
-void board_init_r(gd_t *id, ulong dummy)
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 {
-	struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-
-	/* enable JTAG */
-	writel(0xC0, &pmt->pmt_cfg_ctl);
-
-	debug(">>spl:board_init_r()\n");
-
-	mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
-			CONFIG_SYS_SPL_MALLOC_SIZE);
-
-#ifdef CONFIG_SPL_BOARD_INIT
-	spl_board_init();
-#endif
+	debug("image entry point: 0x%X\n", spl_image->entry_point);
 
-	clock_early_init();
-	serial_init();
-	preloader_console_init();
-
-	start_cpu((u32)CONFIG_SYS_TEXT_BASE);
+	start_cpu((u32)spl_image->entry_point);
 	halt_avp();
-	/* not reached */
-}
-
-int board_usb_init(const void *blob)
-{
-	return 0;
 }
diff --git a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
index dc6ba34..008ae89 100644
--- a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
+++ b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
@@ -48,9 +48,11 @@ SECTIONS
 	.got : { *(.got) }
 
 	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+	#include <u-boot.lst>
+	}
 
 	. = ALIGN(4);
 	__bss_start = .;
diff --git a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
index e9f1227..1bba571 100644
--- a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
+++ b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
@@ -72,10 +72,10 @@ lowlevel_init:
 	 * enable UART for early debug trace
 	 */
 	ldr	r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR)
-	mov	r2, #0xd9
-	str	r2, [r1]		/* 115200 baud */
+	mov	r2, #((25000000+CONFIG_BAUDRATE/2) / CONFIG_BAUDRATE)
+	str	r2, [r1]
 	ldr	r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL)
-	mov	r2, #0x03
+	mov	r2, #KS8695_UART_LINEC_WLEN8
 	str	r2, [r1]		/* 8 data bits, no parity, 1 stop */
 	ldr	r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
 	mov	r2, #0x41
diff --git a/arch/arm/cpu/arm920t/s3c24x0/Makefile b/arch/arm/cpu/arm920t/s3c24x0/Makefile
index 0029700..808ab8f 100644
--- a/arch/arm/cpu/arm920t/s3c24x0/Makefile
+++ b/arch/arm/cpu/arm920t/s3c24x0/Makefile
@@ -29,9 +29,6 @@ COBJS-$(CONFIG_USE_IRQ) += interrupts.o
 COBJS-$(CONFIG_DISPLAY_CPUINFO)	+= cpu_info.o
 COBJS-y	+= speed.o
 COBJS-y	+= timer.o
-COBJS-y	+= usb.o
-COBJS-y	+= usb_ohci.o
-
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
diff --git a/arch/arm/cpu/arm920t/s3c24x0/usb.c b/arch/arm/cpu/arm920t/s3c24x0/usb.c
deleted file mode 100644
index 226a3f6..0000000
--- a/arch/arm/cpu/arm920t/s3c24x0/usb.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * (C) Copyright 2006
- * DENX Software Engineering <mk@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#if defined(CONFIG_USB_OHCI_NEW) && \
-    defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
-    defined(CONFIG_S3C24X0)
-
-#include <asm/arch/s3c24x0_cpu.h>
-#include <asm/io.h>
-
-int usb_cpu_init(void)
-{
-	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-	struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
-
-	/*
-	 * Set the 48 MHz UPLL clocking. Values are taken from
-	 * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
-	 */
-	writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon);
-	/* 1 = use pads related USB for USB host */
-	writel(readl(&gpio->misccr) | 0x8, &gpio->misccr);
-
-	/*
-	 * Enable USB host clock.
-	 */
-	writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
-
-	return 0;
-}
-
-int usb_cpu_stop(void)
-{
-	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-	/* may not want to do this */
-	writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
-	return 0;
-}
-
-int usb_cpu_init_fail(void)
-{
-	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-	writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
-	return 0;
-}
-
-#endif /* defined(CONFIG_USB_OHCI_NEW) && \
-	   defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
-	   defined(CONFIG_S3C24X0) */
diff --git a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c b/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c
deleted file mode 100644
index 944bb32..0000000
--- a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c
+++ /dev/null
@@ -1,1757 +0,0 @@
-/*
- * URB OHCI HCD (Host Controller Driver) for USB on the S3C2400.
- *
- * (C) Copyright 2003
- * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
- *
- * Note: Much of this code has been derived from Linux 2.4
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2002 David Brownell
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-/*
- * IMPORTANT NOTES
- * 1 - this driver is intended for use with USB Mass Storage Devices
- *     (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
- */
-
-#include <common.h>
-/* #include <pci.h> no PCI on the S3C24X0 */
-
-#if defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0)
-
-#include <asm/arch/s3c24x0_cpu.h>
-#include <asm/io.h>
-#include <malloc.h>
-#include <usb.h>
-#include "usb_ohci.h"
-
-#define OHCI_USE_NPS		/* force NoPowerSwitching mode */
-#undef OHCI_VERBOSE_DEBUG	/* not always helpful */
-
-
-/* For initializing controller (mask in an HCFS mode too) */
-#define	OHCI_CONTROL_INIT \
-	(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
-
-#define min_t(type, x, y) \
-	({ type __x = (x); type __y = (y); __x < __y ? __x : __y; })
-
-#undef DEBUG
-#ifdef DEBUG
-#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
-#else
-#define dbg(format, arg...) do {} while(0)
-#endif /* DEBUG */
-#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
-#undef SHOW_INFO
-#ifdef SHOW_INFO
-#define info(format, arg...) printf("INFO: " format "\n", ## arg)
-#else
-#define info(format, arg...) do {} while(0)
-#endif
-
-#define m16_swap(x) swap_16(x)
-#define m32_swap(x) swap_32(x)
-
-/* global struct ohci */
-static struct ohci gohci;
-/* this must be aligned to a 256 byte boundary */
-struct ohci_hcca ghcca[1];
-/* a pointer to the aligned storage */
-struct ohci_hcca *phcca;
-/* this allocates EDs for all possible endpoints */
-struct ohci_device ohci_dev;
-/* urb_priv */
-struct urb_priv urb_priv;
-/* RHSC flag */
-int got_rhsc;
-/* device which was disconnected */
-struct usb_device *devgone;
-/* flag guarding URB transation */
-int urb_finished = 0;
-
-/*-------------------------------------------------------------------------*/
-
-/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
- * The erratum (#4) description is incorrect.  AMD's workaround waits
- * till some bits (mostly reserved) are clear; ok for all revs.
- */
-#define OHCI_QUIRK_AMD756 0xabcd
-#define read_roothub(hc, register, mask) ({ \
-	u32 temp = readl (&hc->regs->roothub.register); \
-	if (hc->flags & OHCI_QUIRK_AMD756) \
-		while (temp & mask) \
-			temp = readl (&hc->regs->roothub.register); \
-	temp; })
-
-static u32 roothub_a(struct ohci *hc)
-{
-	return read_roothub(hc, a, 0xfc0fe000);
-}
-static inline u32 roothub_b(struct ohci *hc)
-{
-	return readl(&hc->regs->roothub.b);
-}
-static inline u32 roothub_status(struct ohci *hc)
-{
-	return readl(&hc->regs->roothub.status);
-}
-static u32 roothub_portstatus(struct ohci *hc, int i)
-{
-	return read_roothub(hc, portstatus[i], 0xffe0fce0);
-}
-
-/* forward declaration */
-static int hc_interrupt(void);
-static void td_submit_job(struct usb_device *dev, unsigned long pipe,
-			  void *buffer, int transfer_len,
-			  struct devrequest *setup, struct urb_priv *urb,
-			  int interval);
-
-/*-------------------------------------------------------------------------*
- * URB support functions
- *-------------------------------------------------------------------------*/
-
-/* free HCD-private data associated with this URB */
-
-static void urb_free_priv(struct urb_priv *urb)
-{
-	int i;
-	int last;
-	struct td *td;
-
-	last = urb->length - 1;
-	if (last >= 0) {
-		for (i = 0; i <= last; i++) {
-			td = urb->td[i];
-			if (td) {
-				td->usb_dev = NULL;
-				urb->td[i] = NULL;
-			}
-		}
-	}
-}
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef DEBUG
-static int sohci_get_current_frame_number(struct usb_device *dev);
-
-/* debug| print the main components of an URB
- * small: 0) header + data packets 1) just header */
-
-static void pkt_print(struct usb_device *dev, unsigned long pipe, void *buffer,
-		      int transfer_len, struct devrequest *setup, char *str,
-		      int small)
-{
-	struct urb_priv *purb = &urb_priv;
-
-	dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
-	    str,
-	    sohci_get_current_frame_number(dev),
-	    usb_pipedevice(pipe),
-	    usb_pipeendpoint(pipe),
-	    usb_pipeout(pipe) ? 'O' : 'I',
-	    usb_pipetype(pipe) < 2 ?
-		(usb_pipeint(pipe) ? "INTR" : "ISOC") :
-		(usb_pipecontrol(pipe) ? "CTRL" : "BULK"),
-	    purb->actual_length, transfer_len, dev->status);
-#ifdef	OHCI_VERBOSE_DEBUG
-	if (!small) {
-		int i, len;
-
-		if (usb_pipecontrol(pipe)) {
-			printf(__FILE__ ": cmd(8):");
-			for (i = 0; i < 8; i++)
-				printf(" %02x", ((__u8 *) setup)[i]);
-			printf("\n");
-		}
-		if (transfer_len > 0 && buffer) {
-			printf(__FILE__ ": data(%d/%d):",
-			       purb->actual_length, transfer_len);
-			len = usb_pipeout(pipe) ?
-			    transfer_len : purb->actual_length;
-			for (i = 0; i < 16 && i < len; i++)
-				printf(" %02x", ((__u8 *) buffer)[i]);
-			printf("%s\n", i < len ? "..." : "");
-		}
-	}
-#endif
-}
-
-/* just for debugging; prints non-empty branches of the
-   int ed tree inclusive iso eds*/
-void ep_print_int_eds(struct ohci *ohci, char *str)
-{
-	int i, j;
-	__u32 *ed_p;
-	for (i = 0; i < 32; i++) {
-		j = 5;
-		ed_p = &(ohci->hcca->int_table[i]);
-		if (*ed_p == 0)
-			continue;
-		printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i);
-		while (*ed_p != 0 && j--) {
-			struct ed *ed = (struct ed *) m32_swap(ed_p);
-			printf(" ed: %4x;", ed->hwINFO);
-			ed_p = &ed->hwNextED;
-		}
-		printf("\n");
-	}
-}
-
-static void ohci_dump_intr_mask(char *label, __u32 mask)
-{
-	dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
-	    label,
-	    mask,
-	    (mask & OHCI_INTR_MIE) ? " MIE" : "",
-	    (mask & OHCI_INTR_OC) ? " OC" : "",
-	    (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
-	    (mask & OHCI_INTR_FNO) ? " FNO" : "",
-	    (mask & OHCI_INTR_UE) ? " UE" : "",
-	    (mask & OHCI_INTR_RD) ? " RD" : "",
-	    (mask & OHCI_INTR_SF) ? " SF" : "",
-	    (mask & OHCI_INTR_WDH) ? " WDH" : "",
-	    (mask & OHCI_INTR_SO) ? " SO" : "");
-}
-
-static void maybe_print_eds(char *label, __u32 value)
-{
-	struct ed *edp = (struct ed *) value;
-
-	if (value) {
-		dbg("%s %08x", label, value);
-		dbg("%08x", edp->hwINFO);
-		dbg("%08x", edp->hwTailP);
-		dbg("%08x", edp->hwHeadP);
-		dbg("%08x", edp->hwNextED);
-	}
-}
-
-static char *hcfs2string(int state)
-{
-	switch (state) {
-	case OHCI_USB_RESET:
-		return "reset";
-	case OHCI_USB_RESUME:
-		return "resume";
-	case OHCI_USB_OPER:
-		return "operational";
-	case OHCI_USB_SUSPEND:
-		return "suspend";
-	}
-	return "?";
-}
-
-/* dump control and status registers */
-static void ohci_dump_status(struct ohci *controller)
-{
-	struct ohci_regs *regs = controller->regs;
-	__u32 temp;
-
-	temp = readl(&regs->revision) & 0xff;
-	if (temp != 0x10)
-		dbg("spec %d.%d", (temp >> 4), (temp & 0x0f));
-
-	temp = readl(&regs->control);
-	dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
-	    (temp & OHCI_CTRL_RWE) ? " RWE" : "",
-	    (temp & OHCI_CTRL_RWC) ? " RWC" : "",
-	    (temp & OHCI_CTRL_IR) ? " IR" : "",
-	    hcfs2string(temp & OHCI_CTRL_HCFS),
-	    (temp & OHCI_CTRL_BLE) ? " BLE" : "",
-	    (temp & OHCI_CTRL_CLE) ? " CLE" : "",
-	    (temp & OHCI_CTRL_IE) ? " IE" : "",
-	    (temp & OHCI_CTRL_PLE) ? " PLE" : "", temp & OHCI_CTRL_CBSR);
-
-	temp = readl(&regs->cmdstatus);
-	dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
-	    (temp & OHCI_SOC) >> 16,
-	    (temp & OHCI_OCR) ? " OCR" : "",
-	    (temp & OHCI_BLF) ? " BLF" : "",
-	    (temp & OHCI_CLF) ? " CLF" : "", (temp & OHCI_HCR) ? " HCR" : "");
-
-	ohci_dump_intr_mask("intrstatus", readl(&regs->intrstatus));
-	ohci_dump_intr_mask("intrenable", readl(&regs->intrenable));
-
-	maybe_print_eds("ed_periodcurrent", readl(&regs->ed_periodcurrent));
-
-	maybe_print_eds("ed_controlhead", readl(&regs->ed_controlhead));
-	maybe_print_eds("ed_controlcurrent", readl(&regs->ed_controlcurrent));
-
-	maybe_print_eds("ed_bulkhead", readl(&regs->ed_bulkhead));
-	maybe_print_eds("ed_bulkcurrent", readl(&regs->ed_bulkcurrent));
-
-	maybe_print_eds("donehead", readl(&regs->donehead));
-}
-
-static void ohci_dump_roothub(struct ohci *controller, int verbose)
-{
-	__u32 temp, ndp, i;
-
-	temp = roothub_a(controller);
-	ndp = (temp & RH_A_NDP);
-
-	if (verbose) {
-		dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
-		    ((temp & RH_A_POTPGT) >> 24) & 0xff,
-		    (temp & RH_A_NOCP) ? " NOCP" : "",
-		    (temp & RH_A_OCPM) ? " OCPM" : "",
-		    (temp & RH_A_DT) ? " DT" : "",
-		    (temp & RH_A_NPS) ? " NPS" : "",
-		    (temp & RH_A_PSM) ? " PSM" : "", ndp);
-		temp = roothub_b(controller);
-		dbg("roothub.b: %08x PPCM=%04x DR=%04x",
-		    temp, (temp & RH_B_PPCM) >> 16, (temp & RH_B_DR)
-		    );
-		temp = roothub_status(controller);
-		dbg("roothub.status: %08x%s%s%s%s%s%s",
-		    temp,
-		    (temp & RH_HS_CRWE) ? " CRWE" : "",
-		    (temp & RH_HS_OCIC) ? " OCIC" : "",
-		    (temp & RH_HS_LPSC) ? " LPSC" : "",
-		    (temp & RH_HS_DRWE) ? " DRWE" : "",
-		    (temp & RH_HS_OCI) ? " OCI" : "",
-		    (temp & RH_HS_LPS) ? " LPS" : "");
-	}
-
-	for (i = 0; i < ndp; i++) {
-		temp = roothub_portstatus(controller, i);
-		dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
-		    i,
-		    temp,
-		    (temp & RH_PS_PRSC) ? " PRSC" : "",
-		    (temp & RH_PS_OCIC) ? " OCIC" : "",
-		    (temp & RH_PS_PSSC) ? " PSSC" : "",
-		    (temp & RH_PS_PESC) ? " PESC" : "",
-		    (temp & RH_PS_CSC) ? " CSC" : "",
-		    (temp & RH_PS_LSDA) ? " LSDA" : "",
-		    (temp & RH_PS_PPS) ? " PPS" : "",
-		    (temp & RH_PS_PRS) ? " PRS" : "",
-		    (temp & RH_PS_POCI) ? " POCI" : "",
-		    (temp & RH_PS_PSS) ? " PSS" : "",
-		    (temp & RH_PS_PES) ? " PES" : "",
-		    (temp & RH_PS_CCS) ? " CCS" : "");
-	}
-}
-
-static void ohci_dump(struct ohci *controller, int verbose)
-{
-	dbg("OHCI controller usb-%s state", controller->slot_name);
-
-	/* dumps some of the state we know about */
-	ohci_dump_status(controller);
-	if (verbose)
-		ep_print_int_eds(controller, "hcca");
-	dbg("hcca frame #%04x", controller->hcca->frame_no);
-	ohci_dump_roothub(controller, 1);
-}
-
-#endif /* DEBUG */
-
-/*-------------------------------------------------------------------------*
- * Interface functions (URB)
- *-------------------------------------------------------------------------*/
-
-/* get a transfer request */
-
-int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
-		     int transfer_len, struct devrequest *setup, int interval)
-{
-	struct ohci *ohci;
-	struct ed *ed;
-	struct urb_priv *purb_priv;
-	int i, size = 0;
-
-	ohci = &gohci;
-
-	/* when controller's hung, permit only roothub cleanup attempts
-	 * such as powering down ports */
-	if (ohci->disabled) {
-		err("sohci_submit_job: EPIPE");
-		return -1;
-	}
-
-	/* if we have an unfinished URB from previous transaction let's
-	 * fail and scream as quickly as possible so as not to corrupt
-	 * further communication */
-	if (!urb_finished) {
-		err("sohci_submit_job: URB NOT FINISHED");
-		return -1;
-	}
-	/* we're about to begin a new transaction here
-	   so mark the URB unfinished */
-	urb_finished = 0;
-
-	/* every endpoint has a ed, locate and fill it */
-	ed = ep_add_ed(dev, pipe);
-	if (!ed) {
-		err("sohci_submit_job: ENOMEM");
-		return -1;
-	}
-
-	/* for the private part of the URB we need the number of TDs (size) */
-	switch (usb_pipetype(pipe)) {
-	case PIPE_BULK:
-		/* one TD for every 4096 Byte */
-		size = (transfer_len - 1) / 4096 + 1;
-		break;
-	case PIPE_CONTROL:
-		/* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
-		size = (transfer_len == 0) ? 2 : (transfer_len - 1) / 4096 + 3;
-		break;
-	}
-
-	if (size >= (N_URB_TD - 1)) {
-		err("need %d TDs, only have %d", size, N_URB_TD);
-		return -1;
-	}
-	purb_priv = &urb_priv;
-	purb_priv->pipe = pipe;
-
-	/* fill the private part of the URB */
-	purb_priv->length = size;
-	purb_priv->ed = ed;
-	purb_priv->actual_length = 0;
-
-	/* allocate the TDs */
-	/* note that td[0] was allocated in ep_add_ed */
-	for (i = 0; i < size; i++) {
-		purb_priv->td[i] = td_alloc(dev);
-		if (!purb_priv->td[i]) {
-			purb_priv->length = i;
-			urb_free_priv(purb_priv);
-			err("sohci_submit_job: ENOMEM");
-			return -1;
-		}
-	}
-
-	if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
-		urb_free_priv(purb_priv);
-		err("sohci_submit_job: EINVAL");
-		return -1;
-	}
-
-	/* link the ed into a chain if is not already */
-	if (ed->state != ED_OPER)
-		ep_link(ohci, ed);
-
-	/* fill the TDs and link it to the ed */
-	td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv,
-		      interval);
-
-	return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef DEBUG
-/* tell us the current USB frame number */
-
-static int sohci_get_current_frame_number(struct usb_device *usb_dev)
-{
-	struct ohci *ohci = &gohci;
-
-	return m16_swap(ohci->hcca->frame_no);
-}
-#endif
-
-/*-------------------------------------------------------------------------*
- * ED handling functions
- *-------------------------------------------------------------------------*/
-
-/* link an ed into one of the HC chains */
-
-static int ep_link(struct ohci *ohci, struct ed *edi)
-{
-	struct ed *ed = edi;
-
-	ed->state = ED_OPER;
-
-	switch (ed->type) {
-	case PIPE_CONTROL:
-		ed->hwNextED = 0;
-		if (ohci->ed_controltail == NULL) {
-			writel((u32)ed, &ohci->regs->ed_controlhead);
-		} else {
-			ohci->ed_controltail->hwNextED = (__u32) m32_swap(ed);
-		}
-		ed->ed_prev = ohci->ed_controltail;
-		if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
-		    !ohci->ed_rm_list[1] && !ohci->sleeping) {
-			ohci->hc_control |= OHCI_CTRL_CLE;
-			writel(ohci->hc_control, &ohci->regs->control);
-		}
-		ohci->ed_controltail = edi;
-		break;
-
-	case PIPE_BULK:
-		ed->hwNextED = 0;
-		if (ohci->ed_bulktail == NULL) {
-			writel((u32)ed, &ohci->regs->ed_bulkhead);
-		} else {
-			ohci->ed_bulktail->hwNextED = (__u32) m32_swap(ed);
-		}
-		ed->ed_prev = ohci->ed_bulktail;
-		if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
-		    !ohci->ed_rm_list[1] && !ohci->sleeping) {
-			ohci->hc_control |= OHCI_CTRL_BLE;
-			writel(ohci->hc_control, &ohci->regs->control);
-		}
-		ohci->ed_bulktail = edi;
-		break;
-	}
-	return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* unlink an ed from one of the HC chains.
- * just the link to the ed is unlinked.
- * the link from the ed still points to another operational ed or 0
- * so the HC can eventually finish the processing of the unlinked ed */
-
-static int ep_unlink(struct ohci *ohci, struct ed *ed)
-{
-	struct ed *next;
-	ed->hwINFO |= m32_swap(OHCI_ED_SKIP);
-
-	switch (ed->type) {
-	case PIPE_CONTROL:
-		if (ed->ed_prev == NULL) {
-			if (!ed->hwNextED) {
-				ohci->hc_control &= ~OHCI_CTRL_CLE;
-				writel(ohci->hc_control, &ohci->regs->control);
-			}
-			writel(m32_swap(*((__u32 *) &ed->hwNextED)),
-			       &ohci->regs->ed_controlhead);
-		} else {
-			ed->ed_prev->hwNextED = ed->hwNextED;
-		}
-		if (ohci->ed_controltail == ed) {
-			ohci->ed_controltail = ed->ed_prev;
-		} else {
-			next = (struct ed *)m32_swap(*((__u32 *)&ed->hwNextED));
-			next->ed_prev = ed->ed_prev;
-		}
-		break;
-
-	case PIPE_BULK:
-		if (ed->ed_prev == NULL) {
-			if (!ed->hwNextED) {
-				ohci->hc_control &= ~OHCI_CTRL_BLE;
-				writel(ohci->hc_control, &ohci->regs->control);
-			}
-			writel(m32_swap(*((__u32 *) &ed->hwNextED)),
-			       &ohci->regs->ed_bulkhead);
-		} else {
-			ed->ed_prev->hwNextED = ed->hwNextED;
-		}
-		if (ohci->ed_bulktail == ed) {
-			ohci->ed_bulktail = ed->ed_prev;
-		} else {
-			next = (struct ed *)m32_swap(*((__u32 *)&ed->hwNextED));
-			next->ed_prev = ed->ed_prev;
-		}
-		break;
-	}
-	ed->state = ED_UNLINK;
-	return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* add/reinit an endpoint; this should be done once at the usb_set_configuration
- * command, but the USB stack is a little bit stateless  so we do it at every
- * transaction. If the state of the ed is ED_NEW then a dummy td is added and
- * the state is changed to ED_UNLINK. In all other cases the state is left
- * unchanged. The ed info fields are setted anyway even though most of them
- * should not change */
-
-static struct ed *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe)
-{
-	struct td *td;
-	struct ed *ed_ret;
-	struct ed *ed;
-
-	ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint(pipe) << 1) |
-				   (usb_pipecontrol(pipe) ? 0 :
-				    usb_pipeout(pipe))];
-
-	if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
-		err("ep_add_ed: pending delete");
-		/* pending delete request */
-		return NULL;
-	}
-
-	if (ed->state == ED_NEW) {
-		ed->hwINFO = m32_swap(OHCI_ED_SKIP);	/* skip ed */
-		/* dummy td; end of td list for ed */
-		td = td_alloc(usb_dev);
-		ed->hwTailP = (__u32) m32_swap(td);
-		ed->hwHeadP = ed->hwTailP;
-		ed->state = ED_UNLINK;
-		ed->type = usb_pipetype(pipe);
-		ohci_dev.ed_cnt++;
-	}
-
-	ed->hwINFO = m32_swap(usb_pipedevice(pipe)
-			      | usb_pipeendpoint(pipe) << 7
-			      | (usb_pipeisoc(pipe) ? 0x8000 : 0)
-			      | (usb_pipecontrol(pipe) ? 0 :
-				 (usb_pipeout(pipe) ? 0x800 : 0x1000))
-			      | usb_pipeslow(pipe) << 13 |
-			      usb_maxpacket(usb_dev, pipe) << 16);
-
-	return ed_ret;
-}
-
-/*-------------------------------------------------------------------------*
- * TD handling functions
- *-------------------------------------------------------------------------*/
-
-/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
-
-static void td_fill(struct ohci *ohci, unsigned int info, void *data, int len,
-		    struct usb_device *dev, int index,
-		    struct urb_priv *urb_priv)
-{
-	struct td *td, *td_pt;
-#ifdef OHCI_FILL_TRACE
-	int i;
-#endif
-
-	if (index > urb_priv->length) {
-		err("index > length");
-		return;
-	}
-	/* use this td as the next dummy */
-	td_pt = urb_priv->td[index];
-	td_pt->hwNextTD = 0;
-
-	/* fill the old dummy TD */
-	td = urb_priv->td[index] =
-	    (struct td *) (m32_swap(urb_priv->ed->hwTailP) & ~0xf);
-
-	td->ed = urb_priv->ed;
-	td->next_dl_td = NULL;
-	td->index = index;
-	td->data = (__u32) data;
-#ifdef OHCI_FILL_TRACE
-	if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
-		for (i = 0; i < len; i++)
-			printf("td->data[%d] %#2x ", i,
-			       ((unsigned char *)td->data)[i]);
-		printf("\n");
-	}
-#endif
-	if (!len)
-		data = 0;
-
-	td->hwINFO = (__u32) m32_swap(info);
-	td->hwCBP = (__u32) m32_swap(data);
-	if (data)
-		td->hwBE = (__u32) m32_swap(data + len - 1);
-	else
-		td->hwBE = 0;
-	td->hwNextTD = (__u32) m32_swap(td_pt);
-
-	/* append to queue */
-	td->ed->hwTailP = td->hwNextTD;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* prepare all TDs of a transfer */
-
-static void td_submit_job(struct usb_device *dev, unsigned long pipe,
-			  void *buffer, int transfer_len,
-			  struct devrequest *setup, struct urb_priv *urb,
-			  int interval)
-{
-	struct ohci *ohci = &gohci;
-	int data_len = transfer_len;
-	void *data;
-	int cnt = 0;
-	__u32 info = 0;
-	unsigned int toggle = 0;
-
-	/* OHCI handles the DATA-toggles itself, we just
-	   use the USB-toggle bits for reseting */
-	if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
-		toggle = TD_T_TOGGLE;
-	} else {
-		toggle = TD_T_DATA0;
-		usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe),
-			      1);
-	}
-	urb->td_cnt = 0;
-	if (data_len)
-		data = buffer;
-	else
-		data = 0;
-
-	switch (usb_pipetype(pipe)) {
-	case PIPE_BULK:
-		info = usb_pipeout(pipe) ? TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN;
-		while (data_len > 4096) {
-			td_fill(ohci, info | (cnt ? TD_T_TOGGLE : toggle), data,
-				4096, dev, cnt, urb);
-			data += 4096;
-			data_len -= 4096;
-			cnt++;
-		}
-		info = usb_pipeout(pipe) ?
-				TD_CC | TD_DP_OUT :
-				TD_CC | TD_R | TD_DP_IN;
-		td_fill(ohci, info | (cnt ? TD_T_TOGGLE : toggle), data,
-			data_len, dev, cnt, urb);
-		cnt++;
-
-		if (!ohci->sleeping)
-			/* start bulk list */
-			writel(OHCI_BLF, &ohci->regs->cmdstatus);
-		break;
-
-	case PIPE_CONTROL:
-		info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
-		td_fill(ohci, info, setup, 8, dev, cnt++, urb);
-		if (data_len > 0) {
-			info = usb_pipeout(pipe) ?
-			    TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 :
-			    TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
-			/* NOTE:  mishandles transfers >8K, some >4K */
-			td_fill(ohci, info, data, data_len, dev, cnt++, urb);
-		}
-		info = usb_pipeout(pipe) ?
-		    TD_CC | TD_DP_IN | TD_T_DATA1 :
-		    TD_CC | TD_DP_OUT | TD_T_DATA1;
-		td_fill(ohci, info, data, 0, dev, cnt++, urb);
-		if (!ohci->sleeping)
-			/* start Control list */
-			writel(OHCI_CLF, &ohci->regs->cmdstatus);
-		break;
-	}
-	if (urb->length != cnt)
-		dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
-}
-
-/*-------------------------------------------------------------------------*
- * Done List handling functions
- *-------------------------------------------------------------------------*/
-
-
-/* calculate the transfer length and update the urb */
-
-static void dl_transfer_length(struct td *td)
-{
-	__u32 tdBE, tdCBP;
-	struct urb_priv *lurb_priv = &urb_priv;
-
-	tdBE = m32_swap(td->hwBE);
-	tdCBP = m32_swap(td->hwCBP);
-
-	if (!(usb_pipecontrol(lurb_priv->pipe) &&
-	      ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
-		if (tdBE != 0) {
-			if (td->hwCBP == 0)
-				lurb_priv->actual_length += tdBE - td->data + 1;
-			else
-				lurb_priv->actual_length += tdCBP - td->data;
-		}
-	}
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* replies to the request have to be on a FIFO basis so
- * we reverse the reversed done-list */
-
-static struct td *dl_reverse_done_list(struct ohci *ohci)
-{
-	__u32 td_list_hc;
-	__u32 tmp;
-	struct td *td_rev = NULL;
-	struct td *td_list = NULL;
-	struct urb_priv *lurb_priv = NULL;
-
-	td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0;
-	ohci->hcca->done_head = 0;
-
-	while (td_list_hc) {
-		td_list = (struct td *) td_list_hc;
-
-		if (TD_CC_GET(m32_swap(td_list->hwINFO))) {
-			lurb_priv = &urb_priv;
-			dbg(" USB-error/status: %x : %p",
-			    TD_CC_GET(m32_swap(td_list->hwINFO)), td_list);
-			if (td_list->ed->hwHeadP & m32_swap(0x1)) {
-				if (lurb_priv &&
-				    ((td_list->index+1) < lurb_priv->length)) {
-					tmp = lurb_priv->length - 1;
-					td_list->ed->hwHeadP =
-						(lurb_priv->td[tmp]->hwNextTD &
-						 m32_swap(0xfffffff0)) |
-						 (td_list->ed->hwHeadP &
-						  m32_swap(0x2));
-					lurb_priv->td_cnt += lurb_priv->length -
-							     td_list->index - 1;
-				} else
-					td_list->ed->hwHeadP &=
-					    m32_swap(0xfffffff2);
-			}
-		}
-
-		td_list->next_dl_td = td_rev;
-		td_rev = td_list;
-		td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0;
-	}
-
-	return td_list;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* td done list */
-static int dl_done_list(struct ohci *ohci, struct td *td_list)
-{
-	struct td *td_list_next = NULL;
-	struct ed *ed;
-	int cc = 0;
-	int stat = 0;
-	/* urb_t *urb; */
-	struct urb_priv *lurb_priv;
-	__u32 tdINFO, edHeadP, edTailP;
-
-	while (td_list) {
-		td_list_next = td_list->next_dl_td;
-
-		lurb_priv = &urb_priv;
-		tdINFO = m32_swap(td_list->hwINFO);
-
-		ed = td_list->ed;
-
-		dl_transfer_length(td_list);
-
-		/* error code of transfer */
-		cc = TD_CC_GET(tdINFO);
-		if (cc != 0) {
-			dbg("ConditionCode %#x", cc);
-			stat = cc_to_error[cc];
-		}
-
-		/* see if this done list makes for all TD's of current URB,
-		 * and mark the URB finished if so */
-		if (++(lurb_priv->td_cnt) == lurb_priv->length) {
-			if ((ed->state & (ED_OPER | ED_UNLINK)))
-				urb_finished = 1;
-			else
-				dbg("dl_done_list: strange.., ED state %x, "
-				    "ed->state\n");
-		} else
-			dbg("dl_done_list: processing TD %x, len %x\n",
-			    lurb_priv->td_cnt, lurb_priv->length);
-
-		if (ed->state != ED_NEW) {
-			edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0;
-			edTailP = m32_swap(ed->hwTailP);
-
-			/* unlink eds if they are not busy */
-			if ((edHeadP == edTailP) && (ed->state == ED_OPER))
-				ep_unlink(ohci, ed);
-		}
-
-		td_list = td_list_next;
-	}
-	return stat;
-}
-
-/*-------------------------------------------------------------------------*
- * Virtual Root Hub
- *-------------------------------------------------------------------------*/
-
-/* Device descriptor */
-static __u8 root_hub_dev_des[] = {
-	0x12,	/*  __u8  bLength; */
-	0x01,	/*  __u8  bDescriptorType; Device */
-	0x10,	/*  __u16 bcdUSB; v1.1 */
-	0x01,
-	0x09,	/*  __u8  bDeviceClass; HUB_CLASSCODE */
-	0x00,	/*  __u8  bDeviceSubClass; */
-	0x00,	/*  __u8  bDeviceProtocol; */
-	0x08,	/*  __u8  bMaxPacketSize0; 8 Bytes */
-	0x00,	/*  __u16 idVendor; */
-	0x00,
-	0x00,	/*  __u16 idProduct; */
-	0x00,
-	0x00,	/*  __u16 bcdDevice; */
-	0x00,
-	0x00,	/*  __u8  iManufacturer; */
-	0x01,	/*  __u8  iProduct; */
-	0x00,	/*  __u8  iSerialNumber; */
-	0x01	/*  __u8  bNumConfigurations; */
-};
-
-/* Configuration descriptor */
-static __u8 root_hub_config_des[] = {
-	0x09,	/*  __u8  bLength; */
-	0x02,	/*  __u8  bDescriptorType; Configuration */
-	0x19,	/*  __u16 wTotalLength; */
-	0x00,
-	0x01,	/*  __u8  bNumInterfaces; */
-	0x01,	/*  __u8  bConfigurationValue; */
-	0x00,	/*  __u8  iConfiguration; */
-	0x40,	/*  __u8  bmAttributes;
-		   Bit 7: Bus-powered, 6: Self-powered,
-		   5 Remote-wakwup, 4..0: resvd */
-	0x00,	/*  __u8  MaxPower; */
-
-	/* interface */
-	0x09,	/*  __u8  if_bLength; */
-	0x04,	/*  __u8  if_bDescriptorType; Interface */
-	0x00,	/*  __u8  if_bInterfaceNumber; */
-	0x00,	/*  __u8  if_bAlternateSetting; */
-	0x01,	/*  __u8  if_bNumEndpoints; */
-	0x09,	/*  __u8  if_bInterfaceClass; HUB_CLASSCODE */
-	0x00,	/*  __u8  if_bInterfaceSubClass; */
-	0x00,	/*  __u8  if_bInterfaceProtocol; */
-	0x00,	/*  __u8  if_iInterface; */
-
-	/* endpoint */
-	0x07,	/*  __u8  ep_bLength; */
-	0x05,	/*  __u8  ep_bDescriptorType; Endpoint */
-	0x81,	/*  __u8  ep_bEndpointAddress; IN Endpoint 1 */
-	0x03,	/*  __u8  ep_bmAttributes; Interrupt */
-	0x02,	/*  __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
-	0x00,
-	0xff	/*  __u8  ep_bInterval; 255 ms */
-};
-
-static unsigned char root_hub_str_index0[] = {
-	0x04,	/*  __u8  bLength; */
-	0x03,	/*  __u8  bDescriptorType; String-descriptor */
-	0x09,	/*  __u8  lang ID */
-	0x04,	/*  __u8  lang ID */
-};
-
-static unsigned char root_hub_str_index1[] = {
-	28,	/*  __u8  bLength; */
-	0x03,	/*  __u8  bDescriptorType; String-descriptor */
-	'O',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'H',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'C',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'I',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	' ',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'R',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'o',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'o',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	't',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	' ',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'H',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'u',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'b',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-};
-
-/* Hub class-specific descriptor is constructed dynamically */
-
-
-/*-------------------------------------------------------------------------*/
-
-#define OK(x)			len = (x); break
-#ifdef DEBUG
-#define WR_RH_STAT(x) \
-{ \
-	info("WR:status %#8x", (x)); \
-	writel((x), &gohci.regs->roothub.status); \
-}
-#define WR_RH_PORTSTAT(x) \
-{ \
-	info("WR:portstatus[%d] %#8x", wIndex-1, (x)); \
-	writel((x), &gohci.regs->roothub.portstatus[wIndex-1]); \
-}
-#else
-#define WR_RH_STAT(x) \
-	writel((x), &gohci.regs->roothub.status)
-#define WR_RH_PORTSTAT(x)\
-	writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
-#endif
-#define RD_RH_STAT	roothub_status(&gohci)
-#define RD_RH_PORTSTAT	roothub_portstatus(&gohci, wIndex-1)
-
-/* request to virtual root hub */
-
-int rh_check_port_status(struct ohci *controller)
-{
-	__u32 temp, ndp, i;
-	int res;
-
-	res = -1;
-	temp = roothub_a(controller);
-	ndp = (temp & RH_A_NDP);
-	for (i = 0; i < ndp; i++) {
-		temp = roothub_portstatus(controller, i);
-		/* check for a device disconnect */
-		if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
-		     (RH_PS_PESC | RH_PS_CSC)) && ((temp & RH_PS_CCS) == 0)) {
-			res = i;
-			break;
-		}
-	}
-	return res;
-}
-
-static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
-			      void *buffer, int transfer_len,
-			      struct devrequest *cmd)
-{
-	void *data = buffer;
-	int leni = transfer_len;
-	int len = 0;
-	int stat = 0;
-	union {
-		__u32 word[4];
-		__u16 hword[8];
-		__u8 byte[16];
-	} datab;
-	__u8 *data_buf = datab.byte;
-	__u16 bmRType_bReq;
-	__u16 wValue;
-	__u16 wIndex;
-	__u16 wLength;
-
-#ifdef DEBUG
-	urb_priv.actual_length = 0;
-	pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)",
-		  usb_pipein(pipe));
-#else
-	mdelay(1);
-#endif
-	if (usb_pipeint(pipe)) {
-		info("Root-Hub submit IRQ: NOT implemented");
-		return 0;
-	}
-
-	bmRType_bReq = cmd->requesttype | (cmd->request << 8);
-	wValue = m16_swap(cmd->value);
-	wIndex = m16_swap(cmd->index);
-	wLength = m16_swap(cmd->length);
-
-	info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
-	     dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
-
-	switch (bmRType_bReq) {
-		/* Request Destination:
-		   without flags: Device,
-		   RH_INTERFACE: interface,
-		   RH_ENDPOINT: endpoint,
-		   RH_CLASS means HUB here,
-		   RH_OTHER | RH_CLASS  almost ever means HUB_PORT here
-		 */
-
-	case RH_GET_STATUS:
-		datab.hword[0] = m16_swap(1);
-		OK(2);
-	case RH_GET_STATUS | RH_INTERFACE:
-		datab.hword[0] = m16_swap(0);
-		OK(2);
-	case RH_GET_STATUS | RH_ENDPOINT:
-		datab.hword[0] = m16_swap(0);
-		OK(2);
-	case RH_GET_STATUS | RH_CLASS:
-		datab.word[0] =
-		    m32_swap(RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
-		OK(4);
-	case RH_GET_STATUS | RH_OTHER | RH_CLASS:
-		datab.word[0] = m32_swap(RD_RH_PORTSTAT);
-		OK(4);
-
-	case RH_CLEAR_FEATURE | RH_ENDPOINT:
-		switch (wValue) {
-		case (RH_ENDPOINT_STALL):
-			OK(0);
-		}
-		break;
-
-	case RH_CLEAR_FEATURE | RH_CLASS:
-		switch (wValue) {
-		case RH_C_HUB_LOCAL_POWER:
-			OK(0);
-		case (RH_C_HUB_OVER_CURRENT):
-			WR_RH_STAT(RH_HS_OCIC);
-			OK(0);
-		}
-		break;
-
-	case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
-		switch (wValue) {
-		case (RH_PORT_ENABLE):
-			WR_RH_PORTSTAT(RH_PS_CCS);
-			OK(0);
-		case (RH_PORT_SUSPEND):
-			WR_RH_PORTSTAT(RH_PS_POCI);
-			OK(0);
-		case (RH_PORT_POWER):
-			WR_RH_PORTSTAT(RH_PS_LSDA);
-			OK(0);
-		case (RH_C_PORT_CONNECTION):
-			WR_RH_PORTSTAT(RH_PS_CSC);
-			OK(0);
-		case (RH_C_PORT_ENABLE):
-			WR_RH_PORTSTAT(RH_PS_PESC);
-			OK(0);
-		case (RH_C_PORT_SUSPEND):
-			WR_RH_PORTSTAT(RH_PS_PSSC);
-			OK(0);
-		case (RH_C_PORT_OVER_CURRENT):
-			WR_RH_PORTSTAT(RH_PS_OCIC);
-			OK(0);
-		case (RH_C_PORT_RESET):
-			WR_RH_PORTSTAT(RH_PS_PRSC);
-			OK(0);
-		}
-		break;
-
-	case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
-		switch (wValue) {
-		case (RH_PORT_SUSPEND):
-			WR_RH_PORTSTAT(RH_PS_PSS);
-			OK(0);
-		case (RH_PORT_RESET):	/* BUG IN HUP CODE ******** */
-			if (RD_RH_PORTSTAT & RH_PS_CCS)
-				WR_RH_PORTSTAT(RH_PS_PRS);
-			OK(0);
-		case (RH_PORT_POWER):
-			WR_RH_PORTSTAT(RH_PS_PPS);
-			OK(0);
-		case (RH_PORT_ENABLE):	/* BUG IN HUP CODE ******** */
-			if (RD_RH_PORTSTAT & RH_PS_CCS)
-				WR_RH_PORTSTAT(RH_PS_PES);
-			OK(0);
-		}
-		break;
-
-	case RH_SET_ADDRESS:
-		gohci.rh.devnum = wValue;
-		OK(0);
-
-	case RH_GET_DESCRIPTOR:
-		switch ((wValue & 0xff00) >> 8) {
-		case (0x01):	/* device descriptor */
-			len = min_t(unsigned int,
-				    leni,
-				    min_t(unsigned int,
-					  sizeof(root_hub_dev_des), wLength));
-			data_buf = root_hub_dev_des;
-			OK(len);
-		case (0x02):	/* configuration descriptor */
-			len = min_t(unsigned int,
-				    leni,
-				    min_t(unsigned int,
-					  sizeof(root_hub_config_des),
-					  wLength));
-			data_buf = root_hub_config_des;
-			OK(len);
-		case (0x03):	/* string descriptors */
-			if (wValue == 0x0300) {
-				len = min_t(unsigned int,
-					    leni,
-					    min_t(unsigned int,
-						  sizeof(root_hub_str_index0),
-						  wLength));
-				data_buf = root_hub_str_index0;
-				OK(len);
-			}
-			if (wValue == 0x0301) {
-				len = min_t(unsigned int,
-					    leni,
-					    min_t(unsigned int,
-						  sizeof(root_hub_str_index1),
-						  wLength));
-				data_buf = root_hub_str_index1;
-				OK(len);
-			}
-		default:
-			stat = USB_ST_STALLED;
-		}
-		break;
-
-	case RH_GET_DESCRIPTOR | RH_CLASS:
-		{
-			__u32 temp = roothub_a(&gohci);
-
-			data_buf[0] = 9;	/* min length; */
-			data_buf[1] = 0x29;
-			data_buf[2] = temp & RH_A_NDP;
-			data_buf[3] = 0;
-			if (temp & RH_A_PSM)
-				/* per-port power switching? */
-				data_buf[3] |= 0x1;
-			if (temp & RH_A_NOCP)
-				/* no overcurrent reporting? */
-				data_buf[3] |= 0x10;
-			else if (temp & RH_A_OCPM)
-				/* per-port overcurrent reporting? */
-				data_buf[3] |= 0x8;
-
-			/* corresponds to data_buf[4-7] */
-			datab.word[1] = 0;
-			data_buf[5] = (temp & RH_A_POTPGT) >> 24;
-			temp = roothub_b(&gohci);
-			data_buf[7] = temp & RH_B_DR;
-			if (data_buf[2] < 7) {
-				data_buf[8] = 0xff;
-			} else {
-				data_buf[0] += 2;
-				data_buf[8] = (temp & RH_B_DR) >> 8;
-				data_buf[10] = data_buf[9] = 0xff;
-			}
-
-			len = min_t(unsigned int, leni,
-				    min_t(unsigned int, data_buf[0], wLength));
-			OK(len);
-		}
-
-	case RH_GET_CONFIGURATION:
-		*(__u8 *) data_buf = 0x01;
-		OK(1);
-
-	case RH_SET_CONFIGURATION:
-		WR_RH_STAT(0x10000);
-		OK(0);
-
-	default:
-		dbg("unsupported root hub command");
-		stat = USB_ST_STALLED;
-	}
-
-#ifdef	DEBUG
-	ohci_dump_roothub(&gohci, 1);
-#else
-	mdelay(1);
-#endif
-
-	len = min_t(int, len, leni);
-	if (data != data_buf)
-		memcpy(data, data_buf, len);
-	dev->act_len = len;
-	dev->status = stat;
-
-#ifdef DEBUG
-	if (transfer_len)
-		urb_priv.actual_length = transfer_len;
-	pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)",
-		  0 /*usb_pipein(pipe) */);
-#else
-	mdelay(1);
-#endif
-
-	return stat;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* common code for handling submit messages - used for all but root hub */
-/* accesses. */
-int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-		      int transfer_len, struct devrequest *setup, int interval)
-{
-	int stat = 0;
-	int maxsize = usb_maxpacket(dev, pipe);
-	int timeout;
-
-	/* device pulled? Shortcut the action. */
-	if (devgone == dev) {
-		dev->status = USB_ST_CRC_ERR;
-		return 0;
-	}
-#ifdef DEBUG
-	urb_priv.actual_length = 0;
-	pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB",
-		  usb_pipein(pipe));
-#else
-	mdelay(1);
-#endif
-	if (!maxsize) {
-		err("submit_common_message: pipesize for pipe %lx is zero",
-		    pipe);
-		return -1;
-	}
-
-	if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) <
-	    0) {
-		err("sohci_submit_job failed");
-		return -1;
-	}
-
-	mdelay(10);
-	/* ohci_dump_status(&gohci); */
-
-	/* allow more time for a BULK device to react - some are slow */
-#define BULK_TO	 5000		/* timeout in milliseconds */
-	if (usb_pipebulk(pipe))
-		timeout = BULK_TO;
-	else
-		timeout = 100;
-
-	/* wait for it to complete */
-	for (;;) {
-		/* check whether the controller is done */
-		stat = hc_interrupt();
-
-		if (stat < 0) {
-			stat = USB_ST_CRC_ERR;
-			break;
-		}
-
-		/* NOTE: since we are not interrupt driven in U-Boot and always
-		 * handle only one URB at a time, we cannot assume the
-		 * transaction finished on the first successful return from
-		 * hc_interrupt().. unless the flag for current URB is set,
-		 * meaning that all TD's to/from device got actually
-		 * transferred and processed. If the current URB is not
-		 * finished we need to re-iterate this loop so as
-		 * hc_interrupt() gets called again as there needs to be some
-		 * more TD's to process still */
-		if ((stat >= 0) && (stat != 0xff) && (urb_finished)) {
-			/* 0xff is returned for an SF-interrupt */
-			break;
-		}
-
-		if (--timeout) {
-			mdelay(1);
-			if (!urb_finished)
-				dbg("\%");
-
-		} else {
-			err("CTL:TIMEOUT ");
-			dbg("submit_common_msg: TO status %x\n", stat);
-			stat = USB_ST_CRC_ERR;
-			urb_finished = 1;
-			break;
-		}
-	}
-
-#if 0
-	/* we got an Root Hub Status Change interrupt */
-	if (got_rhsc) {
-#ifdef DEBUG
-		ohci_dump_roothub(&gohci, 1);
-#endif
-		got_rhsc = 0;
-		/* abuse timeout */
-		timeout = rh_check_port_status(&gohci);
-		if (timeout >= 0) {
-#if 0			/* this does nothing useful, but leave it here
-			   in case that changes */
-			/* the called routine adds 1 to the passed value */
-			usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
-#endif
-			/*
-			 * XXX
-			 * This is potentially dangerous because it assumes
-			 * that only one device is ever plugged in!
-			 */
-			devgone = dev;
-		}
-	}
-#endif
-
-	dev->status = stat;
-	dev->act_len = transfer_len;
-
-#ifdef DEBUG
-	pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)",
-		  usb_pipein(pipe));
-#else
-	mdelay(1);
-#endif
-
-	/* free TDs in urb_priv */
-	urb_free_priv(&urb_priv);
-	return 0;
-}
-
-/* submit routines called from usb.c */
-int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-		    int transfer_len)
-{
-	info("submit_bulk_msg");
-	return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
-}
-
-int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-		       int transfer_len, struct devrequest *setup)
-{
-	int maxsize = usb_maxpacket(dev, pipe);
-
-	info("submit_control_msg");
-#ifdef DEBUG
-	urb_priv.actual_length = 0;
-	pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB",
-		  usb_pipein(pipe));
-#else
-	mdelay(1);
-#endif
-	if (!maxsize) {
-		err("submit_control_message: pipesize for pipe %lx is zero",
-		    pipe);
-		return -1;
-	}
-	if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
-		gohci.rh.dev = dev;
-		/* root hub - redirect */
-		return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
-					  setup);
-	}
-
-	return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
-}
-
-int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-		   int transfer_len, int interval)
-{
-	info("submit_int_msg");
-	return -1;
-}
-
-/*-------------------------------------------------------------------------*
- * HC functions
- *-------------------------------------------------------------------------*/
-
-/* reset the HC and BUS */
-
-static int hc_reset(struct ohci *ohci)
-{
-	int timeout = 30;
-	int smm_timeout = 50;	/* 0,5 sec */
-
-	if (readl(&ohci->regs->control) & OHCI_CTRL_IR) {
-		/* SMM owns the HC - request ownership */
-		writel(OHCI_OCR, &ohci->regs->cmdstatus);
-		info("USB HC TakeOver from SMM");
-		while (readl(&ohci->regs->control) & OHCI_CTRL_IR) {
-			mdelay(10);
-			if (--smm_timeout == 0) {
-				err("USB HC TakeOver failed!");
-				return -1;
-			}
-		}
-	}
-
-	/* Disable HC interrupts */
-	writel(OHCI_INTR_MIE, &ohci->regs->intrdisable);
-
-	dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
-	    ohci->slot_name, readl(&ohci->regs->control));
-
-	/* Reset USB (needed by some controllers) */
-	writel(0, &ohci->regs->control);
-
-	/* HC Reset requires max 10 us delay */
-	writel(OHCI_HCR, &ohci->regs->cmdstatus);
-	while ((readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
-		if (--timeout == 0) {
-			err("USB HC reset timed out!");
-			return -1;
-		}
-		udelay(1);
-	}
-	return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* Start an OHCI controller, set the BUS operational
- * enable interrupts
- * connect the virtual root hub */
-
-static int hc_start(struct ohci *ohci)
-{
-	__u32 mask;
-	unsigned int fminterval;
-
-	ohci->disabled = 1;
-
-	/* Tell the controller where the control and bulk lists are
-	 * The lists are empty now. */
-
-	writel(0, &ohci->regs->ed_controlhead);
-	writel(0, &ohci->regs->ed_bulkhead);
-
-	/* a reset clears this */
-	writel((__u32) ohci->hcca, &ohci->regs->hcca);
-
-	fminterval = 0x2edf;
-	writel((fminterval * 9) / 10, &ohci->regs->periodicstart);
-	fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
-	writel(fminterval, &ohci->regs->fminterval);
-	writel(0x628, &ohci->regs->lsthresh);
-
-	/* start controller operations */
-	ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
-	ohci->disabled = 0;
-	writel(ohci->hc_control, &ohci->regs->control);
-
-	/* disable all interrupts */
-	mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
-		OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
-		OHCI_INTR_OC | OHCI_INTR_MIE);
-	writel(mask, &ohci->regs->intrdisable);
-	/* clear all interrupts */
-	mask &= ~OHCI_INTR_MIE;
-	writel(mask, &ohci->regs->intrstatus);
-	/* Choose the interrupts we care about now  - but w/o MIE */
-	mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
-	writel(mask, &ohci->regs->intrenable);
-
-#ifdef	OHCI_USE_NPS
-	/* required for AMD-756 and some Mac platforms */
-	writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM,
-	       &ohci->regs->roothub.a);
-	writel(RH_HS_LPSC, &ohci->regs->roothub.status);
-#endif /* OHCI_USE_NPS */
-
-	/* POTPGT delay is bits 24-31, in 2 ms units. */
-	mdelay((roothub_a(ohci) >> 23) & 0x1fe);
-
-	/* connect the virtual root hub */
-	ohci->rh.devnum = 0;
-
-	return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* an interrupt happens */
-
-static int hc_interrupt(void)
-{
-	struct ohci *ohci = &gohci;
-	struct ohci_regs *regs = ohci->regs;
-	int ints;
-	int stat = -1;
-
-	if ((ohci->hcca->done_head != 0) &&
-	    !(m32_swap(ohci->hcca->done_head) & 0x01)) {
-
-		ints = OHCI_INTR_WDH;
-
-	} else {
-		ints = readl(&regs->intrstatus);
-		if (ints == ~(u32) 0) {
-			ohci->disabled++;
-			err("%s device removed!", ohci->slot_name);
-			return -1;
-		}
-		ints &= readl(&regs->intrenable);
-		if (ints == 0) {
-			dbg("hc_interrupt: returning..\n");
-			return 0xff;
-		}
-	}
-
-	/* dbg("Interrupt: %x frame: %x", ints,
-	    le16_to_cpu(ohci->hcca->frame_no)); */
-
-	if (ints & OHCI_INTR_RHSC) {
-		got_rhsc = 1;
-		stat = 0xff;
-	}
-
-	if (ints & OHCI_INTR_UE) {
-		ohci->disabled++;
-		err("OHCI Unrecoverable Error, controller usb-%s disabled",
-		    ohci->slot_name);
-		/* e.g. due to PCI Master/Target Abort */
-
-#ifdef	DEBUG
-		ohci_dump(ohci, 1);
-#else
-		mdelay(1);
-#endif
-		/* FIXME: be optimistic, hope that bug won't repeat often. */
-		/* Make some non-interrupt context restart the controller. */
-		/* Count and limit the retries though; either hardware or */
-		/* software errors can go forever... */
-		hc_reset(ohci);
-		return -1;
-	}
-
-	if (ints & OHCI_INTR_WDH) {
-		mdelay(1);
-
-		writel(OHCI_INTR_WDH, &regs->intrdisable);
-		stat = dl_done_list(&gohci, dl_reverse_done_list(&gohci));
-		writel(OHCI_INTR_WDH, &regs->intrenable);
-	}
-
-	if (ints & OHCI_INTR_SO) {
-		dbg("USB Schedule overrun\n");
-		writel(OHCI_INTR_SO, &regs->intrenable);
-		stat = -1;
-	}
-
-	/* FIXME:  this assumes SOF (1/ms) interrupts don't get lost... */
-	if (ints & OHCI_INTR_SF) {
-		unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1;
-		mdelay(1);
-		writel(OHCI_INTR_SF, &regs->intrdisable);
-		if (ohci->ed_rm_list[frame] != NULL)
-			writel(OHCI_INTR_SF, &regs->intrenable);
-		stat = 0xff;
-	}
-
-	writel(ints, &regs->intrstatus);
-	return stat;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/*-------------------------------------------------------------------------*/
-
-/* De-allocate all resources.. */
-
-static void hc_release_ohci(struct ohci *ohci)
-{
-	dbg("USB HC release ohci usb-%s", ohci->slot_name);
-
-	if (!ohci->disabled)
-		hc_reset(ohci);
-}
-
-/*-------------------------------------------------------------------------*/
-
-/*
- * low level initalisation routine, called from usb.c
- */
-static char ohci_inited = 0;
-
-int usb_lowlevel_init(int index, void **controller)
-{
-	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-	struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
-
-	/*
-	 * Set the 48 MHz UPLL clocking. Values are taken from
-	 * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
-	 */
-	clk_power->upllcon = ((40 << 12) + (1 << 4) + 2);
-	gpio->misccr |= 0x8;	/* 1 = use pads related USB for USB host */
-
-	/*
-	 * Enable USB host clock.
-	 */
-	clk_power->clkcon |= (1 << 4);
-
-	memset(&gohci, 0, sizeof(struct ohci));
-	memset(&urb_priv, 0, sizeof(struct urb_priv));
-
-	/* align the storage */
-	if ((__u32) &ghcca[0] & 0xff) {
-		err("HCCA not aligned!!");
-		return -1;
-	}
-	phcca = &ghcca[0];
-	info("aligned ghcca %p", phcca);
-	memset(&ohci_dev, 0, sizeof(struct ohci_device));
-	if ((__u32) &ohci_dev.ed[0] & 0x7) {
-		err("EDs not aligned!!");
-		return -1;
-	}
-	memset(gtd, 0, sizeof(struct td) * (NUM_TD + 1));
-	if ((__u32) gtd & 0x7) {
-		err("TDs not aligned!!");
-		return -1;
-	}
-	ptd = gtd;
-	gohci.hcca = phcca;
-	memset(phcca, 0, sizeof(struct ohci_hcca));
-
-	gohci.disabled = 1;
-	gohci.sleeping = 0;
-	gohci.irq = -1;
-	gohci.regs = (struct ohci_regs *)S3C24X0_USB_HOST_BASE;
-
-	gohci.flags = 0;
-	gohci.slot_name = "s3c2400";
-
-	if (hc_reset(&gohci) < 0) {
-		hc_release_ohci(&gohci);
-		/* Initialization failed */
-		clk_power->clkcon &= ~(1 << 4);
-		return -1;
-	}
-
-	/* FIXME this is a second HC reset; why?? */
-	gohci.hc_control = OHCI_USB_RESET;
-	writel(gohci.hc_control, &gohci.regs->control);
-	mdelay(10);
-
-	if (hc_start(&gohci) < 0) {
-		err("can't start usb-%s", gohci.slot_name);
-		hc_release_ohci(&gohci);
-		/* Initialization failed */
-		clk_power->clkcon &= ~(1 << 4);
-		return -1;
-	}
-#ifdef	DEBUG
-	ohci_dump(&gohci, 1);
-#else
-	mdelay(1);
-#endif
-	ohci_inited = 1;
-	urb_finished = 1;
-
-	return 0;
-}
-
-int usb_lowlevel_stop(int index)
-{
-	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-
-	/* this gets called really early - before the controller has */
-	/* even been initialized! */
-	if (!ohci_inited)
-		return 0;
-	/* TODO release any interrupts, etc. */
-	/* call hc_release_ohci() here ? */
-	hc_reset(&gohci);
-	/* may not want to do this */
-	clk_power->clkcon &= ~(1 << 4);
-	return 0;
-}
-
-#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0) */
diff --git a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.h b/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.h
deleted file mode 100644
index f272d78..0000000
--- a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.h
+++ /dev/null
@@ -1,409 +0,0 @@
-/*
- * URB OHCI HCD (Host Controller Driver) for USB.
- *
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
- *
- * usb-ohci.h
- */
-
-
-static int cc_to_error[16] = {
-
-/* mapping of the OHCI CC status to error codes */
-	/* No  Error  */ 0,
-	/* CRC Error  */ USB_ST_CRC_ERR,
-	/* Bit Stuff  */ USB_ST_BIT_ERR,
-	/* Data Togg  */ USB_ST_CRC_ERR,
-	/* Stall      */ USB_ST_STALLED,
-	/* DevNotResp */ -1,
-	/* PIDCheck   */ USB_ST_BIT_ERR,
-	/* UnExpPID   */ USB_ST_BIT_ERR,
-	/* DataOver   */ USB_ST_BUF_ERR,
-	/* DataUnder  */ USB_ST_BUF_ERR,
-	/* reservd    */ -1,
-	/* reservd    */ -1,
-	/* BufferOver */ USB_ST_BUF_ERR,
-	/* BuffUnder  */ USB_ST_BUF_ERR,
-	/* Not Access */ -1,
-	/* Not Access */ -1
-};
-
-/* ED States */
-#define ED_NEW		0x00
-#define ED_UNLINK	0x01
-#define ED_OPER		0x02
-#define ED_DEL		0x04
-#define ED_URB_DEL	0x08
-
-/* usb_ohci_ed */
-struct ed {
-	__u32 hwINFO;
-	__u32 hwTailP;
-	__u32 hwHeadP;
-	__u32 hwNextED;
-
-	struct ed *ed_prev;
-	__u8 int_period;
-	__u8 int_branch;
-	__u8 int_load;
-	__u8 int_interval;
-	__u8 state;
-	__u8 type;
-	__u16 last_iso;
-	struct ed *ed_rm_list;
-
-	struct usb_device *usb_dev;
-	__u32 unused[3];
-} __attribute__ ((aligned(16)));
-
-/* TD info field */
-#define TD_CC			0xf0000000
-#define TD_CC_GET(td_p)		(((td_p) >> 28) & 0x0f)
-#define TD_CC_SET(td_p, cc) \
-	{(td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)}
-#define TD_EC			0x0C000000
-#define TD_T			0x03000000
-#define TD_T_DATA0		0x02000000
-#define TD_T_DATA1		0x03000000
-#define TD_T_TOGGLE		0x00000000
-#define TD_R			0x00040000
-#define TD_DI			0x00E00000
-#define TD_DI_SET(X)		(((X) & 0x07)<< 21)
-#define TD_DP			0x00180000
-#define TD_DP_SETUP		0x00000000
-#define TD_DP_IN		0x00100000
-#define TD_DP_OUT		0x00080000
-
-#define TD_ISO			0x00010000
-#define TD_DEL			0x00020000
-
-/* CC Codes */
-#define TD_CC_NOERROR		0x00
-#define TD_CC_CRC		0x01
-#define TD_CC_BITSTUFFING	0x02
-#define TD_CC_DATATOGGLEM	0x03
-#define TD_CC_STALL		0x04
-#define TD_DEVNOTRESP		0x05
-#define TD_PIDCHECKFAIL	0x06
-#define TD_UNEXPECTEDPID	0x07
-#define TD_DATAOVERRUN		0x08
-#define TD_DATAUNDERRUN	0x09
-#define TD_BUFFEROVERRUN	0x0C
-#define TD_BUFFERUNDERRUN	0x0D
-#define TD_NOTACCESSED		0x0F
-
-
-#define MAXPSW 1
-
-struct td {
-	__u32 hwINFO;
-	__u32 hwCBP;		/* Current Buffer Pointer */
-	__u32 hwNextTD;		/* Next TD Pointer */
-	__u32 hwBE;		/* Memory Buffer End Pointer */
-
-	__u8 unused;
-	__u8 index;
-	struct ed *ed;
-	struct td *next_dl_td;
-	struct usb_device *usb_dev;
-	int transfer_len;
-	__u32 data;
-
-	__u32 unused2[2];
-} __attribute__ ((aligned(32)));
-
-#define OHCI_ED_SKIP	(1 << 14)
-
-/*
- * The HCCA (Host Controller Communications Area) is a 256 byte
- * structure defined in the OHCI spec. that the host controller is
- * told the base address of.  It must be 256-byte aligned.
- */
-
-#define NUM_INTS 32		/* part of the OHCI standard */
-struct ohci_hcca {
-	__u32 int_table[NUM_INTS];	/* Interrupt ED table */
-	__u16 frame_no;		/* current frame number */
-	__u16 pad1;		/* set to 0 on each frame_no change */
-	__u32 done_head;	/* info returned for an interrupt */
-	u8 reserved_for_hc[116];
-} __attribute__ ((aligned(256)));
-
-/*
- * Maximum number of root hub ports.
- */
-#define MAX_ROOT_PORTS	15	/* maximum OHCI root hub ports */
-
-/*
- * This is the structure of the OHCI controller's memory mapped I/O
- * region.  This is Memory Mapped I/O.	You must use the readl() and
- * writel() macros defined in asm/io.h to access these!!
- */
-struct ohci_regs {
-	/* control and status registers */
-	__u32 revision;
-	__u32 control;
-	__u32 cmdstatus;
-	__u32 intrstatus;
-	__u32 intrenable;
-	__u32 intrdisable;
-	/* memory pointers */
-	__u32 hcca;
-	__u32 ed_periodcurrent;
-	__u32 ed_controlhead;
-	__u32 ed_controlcurrent;
-	__u32 ed_bulkhead;
-	__u32 ed_bulkcurrent;
-	__u32 donehead;
-	/* frame counters */
-	__u32 fminterval;
-	__u32 fmremaining;
-	__u32 fmnumber;
-	__u32 periodicstart;
-	__u32 lsthresh;
-	/* Root hub ports */
-	struct ohci_roothub_regs {
-		__u32 a;
-		__u32 b;
-		__u32 status;
-		__u32 portstatus[MAX_ROOT_PORTS];
-	} roothub;
-} __attribute__ ((aligned(32)));
-
-/* OHCI CONTROL AND STATUS REGISTER MASKS */
-
-/*
- * HcControl (control) register masks
- */
-#define OHCI_CTRL_CBSR	(3 << 0)	/* control/bulk service ratio */
-#define OHCI_CTRL_PLE	(1 << 2)	/* periodic list enable */
-#define OHCI_CTRL_IE	(1 << 3)	/* isochronous enable */
-#define OHCI_CTRL_CLE	(1 << 4)	/* control list enable */
-#define OHCI_CTRL_BLE	(1 << 5)	/* bulk list enable */
-#define OHCI_CTRL_HCFS	(3 << 6)	/* host controller functional state */
-#define OHCI_CTRL_IR	(1 << 8)	/* interrupt routing */
-#define OHCI_CTRL_RWC	(1 << 9)	/* remote wakeup connected */
-#define OHCI_CTRL_RWE	(1 << 10)	/* remote wakeup enable */
-
-/* pre-shifted values for HCFS */
-#	define OHCI_USB_RESET	(0 << 6)
-#	define OHCI_USB_RESUME	(1 << 6)
-#	define OHCI_USB_OPER	(2 << 6)
-#	define OHCI_USB_SUSPEND	(3 << 6)
-
-/*
- * HcCommandStatus (cmdstatus) register masks
- */
-#define OHCI_HCR	(1 << 0)	/* host controller reset */
-#define OHCI_CLF	(1 << 1)	/* control list filled */
-#define OHCI_BLF	(1 << 2)	/* bulk list filled */
-#define OHCI_OCR	(1 << 3)	/* ownership change request */
-#define OHCI_SOC	(3 << 16)	/* scheduling overrun count */
-
-/*
- * masks used with interrupt registers:
- * HcInterruptStatus (intrstatus)
- * HcInterruptEnable (intrenable)
- * HcInterruptDisable (intrdisable)
- */
-#define OHCI_INTR_SO	(1 << 0)	/* scheduling overrun */
-#define OHCI_INTR_WDH	(1 << 1)	/* writeback of done_head */
-#define OHCI_INTR_SF	(1 << 2)	/* start frame */
-#define OHCI_INTR_RD	(1 << 3)	/* resume detect */
-#define OHCI_INTR_UE	(1 << 4)	/* unrecoverable error */
-#define OHCI_INTR_FNO	(1 << 5)	/* frame number overflow */
-#define OHCI_INTR_RHSC	(1 << 6)	/* root hub status change */
-#define OHCI_INTR_OC	(1 << 30)	/* ownership change */
-#define OHCI_INTR_MIE	(1 << 31)	/* master interrupt enable */
-
-/* Virtual Root HUB */
-struct virt_root_hub {
-	int devnum;		/* Address of Root Hub endpoint */
-	void *dev;		/* was urb */
-	void *int_addr;
-	int send;
-	int interval;
-};
-
-/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
-
-/* destination of request */
-#define RH_INTERFACE		0x01
-#define RH_ENDPOINT		0x02
-#define RH_OTHER		0x03
-
-#define RH_CLASS		0x20
-#define RH_VENDOR		0x40
-
-/* Requests: bRequest << 8 | bmRequestType */
-#define RH_GET_STATUS		0x0080
-#define RH_CLEAR_FEATURE	0x0100
-#define RH_SET_FEATURE		0x0300
-#define RH_SET_ADDRESS		0x0500
-#define RH_GET_DESCRIPTOR	0x0680
-#define RH_SET_DESCRIPTOR	0x0700
-#define RH_GET_CONFIGURATION	0x0880
-#define RH_SET_CONFIGURATION	0x0900
-#define RH_GET_STATE		0x0280
-#define RH_GET_INTERFACE	0x0A80
-#define RH_SET_INTERFACE	0x0B00
-#define RH_SYNC_FRAME		0x0C80
-/* Our Vendor Specific Request */
-#define RH_SET_EP		0x2000
-
-
-/* Hub port features */
-#define RH_PORT_CONNECTION	0x00
-#define RH_PORT_ENABLE		0x01
-#define RH_PORT_SUSPEND		0x02
-#define RH_PORT_OVER_CURRENT	0x03
-#define RH_PORT_RESET		0x04
-#define RH_PORT_POWER		0x08
-#define RH_PORT_LOW_SPEED	0x09
-
-#define RH_C_PORT_CONNECTION	0x10
-#define RH_C_PORT_ENABLE	0x11
-#define RH_C_PORT_SUSPEND	0x12
-#define RH_C_PORT_OVER_CURRENT	0x13
-#define RH_C_PORT_RESET		0x14
-
-/* Hub features */
-#define RH_C_HUB_LOCAL_POWER	0x00
-#define RH_C_HUB_OVER_CURRENT	0x01
-
-#define RH_DEVICE_REMOTE_WAKEUP 0x00
-#define RH_ENDPOINT_STALL	0x01
-
-#define RH_ACK			0x01
-#define RH_REQ_ERR		-1
-#define RH_NACK			0x00
-
-
-/* OHCI ROOT HUB REGISTER MASKS */
-
-/* roothub.portstatus [i] bits */
-#define RH_PS_CCS		0x00000001 /* current connect status */
-#define RH_PS_PES		0x00000002 /* port enable status */
-#define RH_PS_PSS		0x00000004 /* port suspend status */
-#define RH_PS_POCI		0x00000008 /* port over current indicator */
-#define RH_PS_PRS		0x00000010 /* port reset status */
-#define RH_PS_PPS		0x00000100 /* port power status */
-#define RH_PS_LSDA		0x00000200 /* low speed device attached */
-#define RH_PS_CSC		0x00010000 /* connect status change */
-#define RH_PS_PESC		0x00020000 /* port enable status change */
-#define RH_PS_PSSC		0x00040000 /* port suspend status change */
-#define RH_PS_OCIC		0x00080000 /* over current indicator change */
-#define RH_PS_PRSC		0x00100000 /* port reset status change */
-
-/* roothub.status bits */
-#define RH_HS_LPS		0x00000001 /* local power status */
-#define RH_HS_OCI		0x00000002 /* over current indicator */
-#define RH_HS_DRWE		0x00008000 /* device remote wakeup enable */
-#define RH_HS_LPSC		0x00010000 /* local power status change */
-#define RH_HS_OCIC		0x00020000 /* over current indicator change */
-#define RH_HS_CRWE		0x80000000 /* clear remote wakeup enable */
-
-/* roothub.b masks */
-#define RH_B_DR			0x0000ffff /* device removable flags */
-#define RH_B_PPCM		0xffff0000 /* port power control mask */
-
-/* roothub.a masks */
-#define	RH_A_NDP		(0xff << 0)  /* number of downstream ports */
-#define	RH_A_PSM		(1 << 8)     /* power switching mode */
-#define	RH_A_NPS		(1 << 9)     /* no power switching */
-#define	RH_A_DT			(1 << 10)    /* device type (mbz) */
-#define	RH_A_OCPM		(1 << 11)    /* over current protection mode */
-#define	RH_A_NOCP		(1 << 12)    /* no over current protection */
-#define	RH_A_POTPGT		(0xff << 24) /* power on to power good time */
-
-/* urb */
-#define N_URB_TD 48
-struct urb_priv {
-	struct ed *ed;
-	__u16 length;		/* number of tds associated with this request */
-	__u16 td_cnt;		/* number of tds already serviced */
-	int state;
-	unsigned long pipe;
-	int actual_length;
-	struct td *td[N_URB_TD];	/* list pointer to all corresponding TDs
-					   associated with this request */
-};
-#define URB_DEL 1
-
-/*
- * This is the full ohci controller description
- *
- * Note how the "proper" USB information is just
- * a subset of what the full implementation needs. (Linus)
- */
-
-
-struct ohci {
-	struct ohci_hcca *hcca;	/* hcca */
-	/*dma_addr_t hcca_dma; */
-
-	int irq;
-	int disabled;		/* e.g. got a UE, we're hung */
-	int sleeping;
-	unsigned long flags;	/* for HC bugs */
-
-	struct ohci_regs *regs;	/* OHCI controller's memory */
-
-	struct ed *ed_rm_list[2];  /* lists of all endpoints to be removed */
-	struct ed *ed_bulktail;    /* last endpoint of bulk list */
-	struct ed *ed_controltail; /* last endpoint of control list */
-	int intrstatus;
-	__u32 hc_control;	/* copy of the hc control reg */
-	struct usb_device *dev[32];
-	struct virt_root_hub rh;
-
-	const char *slot_name;
-};
-
-#define NUM_EDS 8		/* num of preallocated endpoint descriptors */
-
-struct ohci_device {
-	struct ed ed[NUM_EDS];
-	int ed_cnt;
-};
-
-/* hcd */
-/* endpoint */
-static int ep_link(struct ohci *ohci, struct ed *ed);
-static int ep_unlink(struct ohci *ohci, struct ed *ed);
-static struct ed *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe);
-
-/*-------------------------------------------------------------------------*/
-
-/* we need more TDs than EDs */
-#define NUM_TD 64
-
-/* +1 so we can align the storage */
-struct td gtd[NUM_TD + 1];
-
-/* pointers to aligned storage */
-struct td *ptd;
-
-/* TDs ... */
-static inline struct td *td_alloc(struct usb_device *usb_dev)
-{
-	int i;
-	struct td *td;
-
-	td = NULL;
-	for (i = 0; i < NUM_TD; i++) {
-		if (ptd[i].usb_dev == NULL) {
-			td = &ptd[i];
-			td->usb_dev = usb_dev;
-			break;
-		}
-	}
-
-	return td;
-}
-
-static inline void ed_free(struct ed *ed)
-{
-	ed->usb_dev = NULL;
-}
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
index 6d77219..9348552 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
@@ -118,6 +118,21 @@ void at91_serial2_hw_init(void)
 	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
 }
 
+void at91_mci_hw_init(void)
+{
+	/* Initialize the MCI0 */
+	at91_set_a_periph(AT91_PIO_PORTA, 17, 1);	/* MCCK */
+	at91_set_a_periph(AT91_PIO_PORTA, 16, 1);	/* MCCDA */
+	at91_set_a_periph(AT91_PIO_PORTA, 15, 1);	/* MCDA0 */
+	at91_set_a_periph(AT91_PIO_PORTA, 18, 1);	/* MCDA1 */
+	at91_set_a_periph(AT91_PIO_PORTA, 19, 1);	/* MCDA2 */
+	at91_set_a_periph(AT91_PIO_PORTA, 20, 1);	/* MCDA3 */
+
+	/* Enable clock for MCI0 */
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer);
+}
+
 #ifdef CONFIG_ATMEL_SPI
 void at91_spi0_hw_init(unsigned long cs_mask)
 {
diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
index f8ea38c..6dc681a 100644
--- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
@@ -50,9 +50,10 @@ SECTIONS
 	}
 
 	. = ALIGN(4);
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
+
+	.u_boot_list : {
+		#include <u-boot.lst>
+	}
 
 	. = ALIGN(4);
 
diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
index afd3381..f3bd5e7 100644
--- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
@@ -50,9 +50,10 @@ SECTIONS
 	}
 
 	. = ALIGN(4);
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
+
+	.u_boot_list : {
+		#include <u-boot.lst>
+	}
 
 	. = ALIGN(4);
 
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile
index 7768912..74875b3 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -21,6 +21,7 @@ COBJS	+= sys_info.o
 COBJS	+= ddr.o
 COBJS	+= emif4.o
 COBJS	+= board.o
+COBJS	+= mux.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 978b184..e4c123c 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -36,9 +36,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
-
 static const struct gpio_bank gpio_bank_am33xx[4] = {
 	{ (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
 	{ (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
@@ -48,153 +45,11 @@ static const struct gpio_bank gpio_bank_am33xx[4] = {
 
 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
 
-/* MII mode defines */
-#define MII_MODE_ENABLE		0x0
-#define RGMII_MODE_ENABLE	0xA
-
-/* GPIO that controls power to DDR on EVM-SK */
-#define GPIO_DDR_VTT_EN		7
-
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-static struct am335x_baseboard_id __attribute__((section (".data"))) header;
-
-static inline int board_is_bone(void)
-{
-	return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
-}
-
-static inline int board_is_evm_sk(void)
-{
-	return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
-}
-
-/*
- * Read header information from EEPROM into global structure.
- */
-static int read_eeprom(void)
-{
-	/* Check if baseboard eeprom is available */
-	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
-		puts("Could not probe the EEPROM; something fundamentally "
-			"wrong on the I2C bus.\n");
-		return -ENODEV;
-	}
-
-	/* read the eeprom using i2c */
-	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
-							sizeof(header))) {
-		puts("Could not read the EEPROM; something fundamentally"
-			" wrong on the I2C bus.\n");
-		return -EIO;
-	}
-
-	if (header.magic != 0xEE3355AA) {
-		/*
-		 * read the eeprom using i2c again,
-		 * but use only a 1 byte address
-		 */
-		if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
-					(uchar *)&header, sizeof(header))) {
-			puts("Could not read the EEPROM; something "
-				"fundamentally wrong on the I2C bus.\n");
-			return -EIO;
-		}
-
-		if (header.magic != 0xEE3355AA) {
-			printf("Incorrect magic number (0x%x) in EEPROM\n",
-					header.magic);
-			return -EINVAL;
-		}
-	}
-
-	return 0;
-}
-
-/* UART Defines */
-#ifdef CONFIG_SPL_BUILD
-#define UART_RESET		(0x1 << 1)
-#define UART_CLK_RUNNING_MASK	0x1
-#define UART_SMART_IDLE_EN	(0x1 << 0x3)
-#endif
-
-/*
- * Determine what type of DDR we have.
- */
-static short inline board_memory_type(void)
-{
-	/* The following boards are known to use DDR3. */
-	if (board_is_evm_sk())
-		return EMIF_REG_SDRAM_TYPE_DDR3;
-
-	return EMIF_REG_SDRAM_TYPE_DDR2;
-}
-
-/*
- * early system init of muxing and clocks.
- */
-void s_init(void)
-{
-	/* WDT1 is already running when the bootloader gets control
-	 * Disable it to avoid "random" resets
-	 */
-	writel(0xAAAA, &wdtimer->wdtwspr);
-	while (readl(&wdtimer->wdtwwps) != 0x0)
-		;
-	writel(0x5555, &wdtimer->wdtwspr);
-	while (readl(&wdtimer->wdtwwps) != 0x0)
-		;
-
-#ifdef CONFIG_SPL_BUILD
-	/* Setup the PLLs and the clocks for the peripherals */
-	pll_init();
-
-	/* UART softreset */
-	u32 regVal;
-
-	enable_uart0_pin_mux();
-
-	regVal = readl(&uart_base->uartsyscfg);
-	regVal |= UART_RESET;
-	writel(regVal, &uart_base->uartsyscfg);
-	while ((readl(&uart_base->uartsyssts) &
-		UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
-		;
-
-	/* Disable smart idle */
-	regVal = readl(&uart_base->uartsyscfg);
-	regVal |= UART_SMART_IDLE_EN;
-	writel(regVal, &uart_base->uartsyscfg);
-
-	gd = &gdata;
-
-	preloader_console_init();
-
-	/* Initalize the board header */
-	enable_i2c0_pin_mux();
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-	if (read_eeprom() < 0)
-		puts("Could not get board ID.\n");
-
-	enable_board_pin_mux(&header);
-	if (board_is_evm_sk()) {
-		/*
-		 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
-		 * This is safe enough to do on older revs.
-		 */
-		gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
-		gpio_direction_output(GPIO_DDR_VTT_EN, 1);
-	}
-
-	config_ddr(board_memory_type());
-#endif
-}
-
 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
-int board_mmc_init(bd_t *bis)
+int cpu_mmc_init(bd_t *bis)
 {
 	int ret;
-	
+
 	ret = omap_mmc_init(0, 0, 0);
 	if (ret)
 		return ret;
@@ -208,93 +63,3 @@ void setup_clocks_for_console(void)
 	/* Not yet implemented */
 	return;
 }
-
-/*
- * Basic board specific setup.  Pinmux has been handled already.
- */
-int board_init(void)
-{
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-	if (read_eeprom() < 0)
-		puts("Could not get board ID.\n");
-
-	gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
-
-	return 0;
-}
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-static void cpsw_control(int enabled)
-{
-	/* VTP can be added here */
-
-	return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
-	{
-		.slave_reg_ofs	= 0x208,
-		.sliver_reg_ofs	= 0xd80,
-		.phy_id		= 0,
-	},
-	{
-		.slave_reg_ofs	= 0x308,
-		.sliver_reg_ofs	= 0xdc0,
-		.phy_id		= 1,
-	},
-};
-
-static struct cpsw_platform_data cpsw_data = {
-	.mdio_base		= AM335X_CPSW_MDIO_BASE,
-	.cpsw_base		= AM335X_CPSW_BASE,
-	.mdio_div		= 0xff,
-	.channels		= 8,
-	.cpdma_reg_ofs		= 0x800,
-	.slaves			= 1,
-	.slave_data		= cpsw_slaves,
-	.ale_reg_ofs		= 0xd00,
-	.ale_entries		= 1024,
-	.host_port_reg_ofs	= 0x108,
-	.hw_stats_reg_ofs	= 0x900,
-	.mac_control		= (1 << 5),
-	.control		= cpsw_control,
-	.host_port_num		= 0,
-	.version		= CPSW_CTRL_VERSION_2,
-};
-
-int board_eth_init(bd_t *bis)
-{
-	uint8_t mac_addr[6];
-	uint32_t mac_hi, mac_lo;
-
-	if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
-		debug("<ethaddr> not set. Reading from E-fuse\n");
-		/* try reading mac address from efuse */
-		mac_lo = readl(&cdev->macid0l);
-		mac_hi = readl(&cdev->macid0h);
-		mac_addr[0] = mac_hi & 0xFF;
-		mac_addr[1] = (mac_hi & 0xFF00) >> 8;
-		mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
-		mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
-		mac_addr[4] = mac_lo & 0xFF;
-		mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
-		if (is_valid_ether_addr(mac_addr))
-			eth_setenv_enetaddr("ethaddr", mac_addr);
-		else
-			return -1;
-	}
-
-	if (board_is_bone()) {
-		writel(MII_MODE_ENABLE, &cdev->miisel);
-		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
-				PHY_INTERFACE_MODE_MII;
-	} else {
-		writel(RGMII_MODE_ENABLE, &cdev->miisel);
-		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
-				PHY_INTERFACE_MODE_RGMII;
-	}
-
-	return cpsw_register(&cpsw_data);
-}
-#endif
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
index 2b19506..bc2abb6 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -44,6 +44,7 @@
 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
 const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
 const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
+const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
 
 static void enable_interface_clocks(void)
 {
@@ -114,6 +115,41 @@ static void enable_per_clocks(void)
 	while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
 		;
 
+	/* UART1 */
+#ifdef CONFIG_SERIAL2
+	writel(PRCM_MOD_EN, &cmper->uart1clkctrl);
+	while (readl(&cmper->uart1clkctrl) != PRCM_MOD_EN)
+		;
+#endif /* CONFIG_SERIAL2 */
+
+	/* UART2 */
+#ifdef CONFIG_SERIAL3
+	writel(PRCM_MOD_EN, &cmper->uart2clkctrl);
+	while (readl(&cmper->uart2clkctrl) != PRCM_MOD_EN)
+		;
+#endif /* CONFIG_SERIAL3 */
+
+	/* UART3 */
+#ifdef CONFIG_SERIAL4
+	writel(PRCM_MOD_EN, &cmper->uart3clkctrl);
+	while (readl(&cmper->uart3clkctrl) != PRCM_MOD_EN)
+		;
+#endif /* CONFIG_SERIAL4 */
+
+	/* UART4 */
+#ifdef CONFIG_SERIAL5
+	writel(PRCM_MOD_EN, &cmper->uart4clkctrl);
+	while (readl(&cmper->uart4clkctrl) != PRCM_MOD_EN)
+		;
+#endif /* CONFIG_SERIAL5 */
+
+	/* UART5 */
+#ifdef CONFIG_SERIAL6
+	writel(PRCM_MOD_EN, &cmper->uart5clkctrl);
+	while (readl(&cmper->uart5clkctrl) != PRCM_MOD_EN)
+		;
+#endif /* CONFIG_SERIAL6 */
+
 	/* MMC0*/
 	writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
 	while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
@@ -153,6 +189,11 @@ static void enable_per_clocks(void)
 	writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
 	while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
 		;
+
+	/* RTC */
+	writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl);
+	while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN)
+		;
 }
 
 static void mpu_pll_config(void)
diff --git a/arch/arm/cpu/armv7/am33xx/config.mk b/arch/arm/cpu/armv7/am33xx/config.mk
index 5750bbd..babf0eb 100644
--- a/arch/arm/cpu/armv7/am33xx/config.mk
+++ b/arch/arm/cpu/armv7/am33xx/config.mk
@@ -13,6 +13,7 @@
 #
 ifdef CONFIG_SPL_BUILD
 ALL-y	+= $(OBJTREE)/MLO
+ALL-$(CONFIG_SPL_SPI_SUPPORT) += $(OBJTREE)/MLO.byteswap
 else
 ALL-y	+= $(obj)u-boot.img
 endif
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index b2d7c0d..01e3a52 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -47,78 +47,6 @@ void dram_init_banksize(void)
 static struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
 
-static const struct ddr_data ddr2_data = {
-	.datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
-				|(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
-	.datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
-				|(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
-	.datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
-				|(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
-	.datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
-				|(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
-	.datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
-				|(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
-	.datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
-				|(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
-	.datauserank0delay = DDR2_PHY_RANK0_DELAY,
-	.datadldiff0 = PHY_DLL_LOCK_DIFF,
-};
-
-static const struct cmd_control ddr2_cmd_ctrl_data = {
-	.cmd0csratio = DDR2_RATIO,
-	.cmd0dldiff = DDR2_DLL_LOCK_DIFF,
-	.cmd0iclkout = DDR2_INVERT_CLKOUT,
-
-	.cmd1csratio = DDR2_RATIO,
-	.cmd1dldiff = DDR2_DLL_LOCK_DIFF,
-	.cmd1iclkout = DDR2_INVERT_CLKOUT,
-
-	.cmd2csratio = DDR2_RATIO,
-	.cmd2dldiff = DDR2_DLL_LOCK_DIFF,
-	.cmd2iclkout = DDR2_INVERT_CLKOUT,
-};
-
-static const struct emif_regs ddr2_emif_reg_data = {
-	.sdram_config = DDR2_EMIF_SDCFG,
-	.ref_ctrl = DDR2_EMIF_SDREF,
-	.sdram_tim1 = DDR2_EMIF_TIM1,
-	.sdram_tim2 = DDR2_EMIF_TIM2,
-	.sdram_tim3 = DDR2_EMIF_TIM3,
-	.emif_ddr_phy_ctlr_1 = DDR2_EMIF_READ_LATENCY,
-};
-
-static const struct ddr_data ddr3_data = {
-	.datardsratio0 = DDR3_RD_DQS,
-	.datawdsratio0 = DDR3_WR_DQS,
-	.datafwsratio0 = DDR3_PHY_FIFO_WE,
-	.datawrsratio0 = DDR3_PHY_WR_DATA,
-	.datadldiff0 = PHY_DLL_LOCK_DIFF,
-};
-
-static const struct cmd_control ddr3_cmd_ctrl_data = {
-	.cmd0csratio = DDR3_RATIO,
-	.cmd0dldiff = DDR3_DLL_LOCK_DIFF,
-	.cmd0iclkout = DDR3_INVERT_CLKOUT,
-
-	.cmd1csratio = DDR3_RATIO,
-	.cmd1dldiff = DDR3_DLL_LOCK_DIFF,
-	.cmd1iclkout = DDR3_INVERT_CLKOUT,
-
-	.cmd2csratio = DDR3_RATIO,
-	.cmd2dldiff = DDR3_DLL_LOCK_DIFF,
-	.cmd2iclkout = DDR3_INVERT_CLKOUT,
-};
-
-static struct emif_regs ddr3_emif_reg_data = {
-	.sdram_config = DDR3_EMIF_SDCFG,
-	.ref_ctrl = DDR3_EMIF_SDREF,
-	.sdram_tim1 = DDR3_EMIF_TIM1,
-	.sdram_tim2 = DDR3_EMIF_TIM2,
-	.sdram_tim3 = DDR3_EMIF_TIM3,
-	.zq_config = DDR3_ZQ_CFG,
-	.emif_ddr_phy_ctlr_1 = DDR3_EMIF_READ_LATENCY,
-};
-
 static void config_vtp(void)
 {
 	writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
@@ -134,46 +62,26 @@ static void config_vtp(void)
 		;
 }
 
-void config_ddr(short ddr_type)
+void config_ddr(unsigned int pll, unsigned int ioctrl,
+		const struct ddr_data *data, const struct cmd_control *ctrl,
+		const struct emif_regs *regs)
 {
-	int ddr_pll, ioctrl_val;
-	const struct emif_regs *emif_regs;
-	const struct ddr_data *ddr_data;
-	const struct cmd_control *cmd_ctrl_data;
-
-	if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
-		ddr_pll = 266;
-		cmd_ctrl_data = &ddr2_cmd_ctrl_data;
-		ddr_data = &ddr2_data;
-		ioctrl_val = DDR2_IOCTRL_VALUE;
-		emif_regs = &ddr2_emif_reg_data;
-	} else if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR3) {
-		ddr_pll = 303;
-		cmd_ctrl_data = &ddr3_cmd_ctrl_data;
-		ddr_data = &ddr3_data;
-		ioctrl_val = DDR3_IOCTRL_VALUE;
-		emif_regs = &ddr3_emif_reg_data;
-	} else {
-		puts("Unknown memory type");
-		hang();
-	}
-
 	enable_emif_clocks();
-	ddr_pll_config(ddr_pll);
+	ddr_pll_config(pll);
 	config_vtp();
-	config_cmd_ctrl(cmd_ctrl_data);
+	config_cmd_ctrl(ctrl);
 
-	config_ddr_data(0, ddr_data);
-	config_ddr_data(1, ddr_data);
+	config_ddr_data(0, data);
+	config_ddr_data(1, data);
 
-	config_io_ctrl(ioctrl_val);
+	config_io_ctrl(ioctrl);
 
 	/* Set CKE to be controlled by EMIF/DDR PHY */
 	writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
 
 	/* Program EMIF instance */
-	config_ddr_phy(emif_regs);
-	set_sdram_timings(emif_regs);
-	config_sdram(emif_regs);
+	config_ddr_phy(regs);
+	set_sdram_timings(regs);
+	config_sdram(regs);
 }
 #endif
diff --git a/arch/arm/cpu/armv7/am33xx/mux.c b/arch/arm/cpu/armv7/am33xx/mux.c
new file mode 100644
index 0000000..2ded472
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/mux.c
@@ -0,0 +1,33 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+/*
+ * Configure the pin mux for the module
+ */
+void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux)
+{
+	int i;
+
+	if (!mod_pin_mux)
+		return;
+
+	for (i = 0; mod_pin_mux[i].reg_offset != -1; i++)
+		MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset);
+}
diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
index 1d8efb2..9979c30 100644
--- a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
+++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
@@ -47,6 +47,11 @@ SECTIONS
 
 	. = ALIGN(4);
 	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+	.u_boot_list : {
+		#include <u-boot.lst>
+	}
+
 	. = ALIGN(4);
 	__image_copy_end = .;
 	_end = .;
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 9cee1d9..f3cd81a 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -50,7 +50,9 @@ DECLARE_GLOBAL_DATA_PTR;
 /* Declarations */
 extern omap3_sysinfo sysinfo;
 static void omap3_setup_aux_cr(void);
+#ifndef CONFIG_SYS_L2CACHE_OFF
 static void omap3_invalidate_l2_cache_secure(void);
+#endif
 
 static const struct gpio_bank gpio_bank_34xx[6] = {
 	{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
@@ -410,19 +412,6 @@ static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
 	}
 }
 
-static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
-{
-	u32 acr;
-
-	/* Read ACR */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
-	acr &= ~clear_bits;
-	acr |= set_bits;
-
-	/* Write ACR - affects non-secure banked bits */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
-}
-
 static void omap3_setup_aux_cr(void)
 {
 	/* Workaround for Cortex-A8 errata: #454179 #430973
@@ -436,6 +425,19 @@ static void omap3_setup_aux_cr(void)
 }
 
 #ifndef CONFIG_SYS_L2CACHE_OFF
+static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
+{
+	u32 acr;
+
+	/* Read ACR */
+	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
+	acr &= ~clear_bits;
+	acr |= set_bits;
+
+	/* Write ACR - affects non-secure banked bits */
+	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
+}
+
 /* Invalidate the entire L2 cache from secure mode */
 static void omap3_invalidate_l2_cache_secure(void)
 {
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
index 944238b..84216eb 100644
--- a/arch/arm/cpu/armv7/socfpga/spl.c
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -21,7 +21,6 @@
 #include <asm/utils.h>
 #include <version.h>
 #include <image.h>
-#include <malloc.h>
 #include <asm/arch/reset_manager.h>
 #include <spl.h>
 
@@ -37,9 +36,6 @@ u32 spl_boot_device(void)
  */
 void spl_board_init(void)
 {
-	/* init timer for enabling delay function */
-	timer_init();
-
 	/* de-assert reset for peripherals and bridges based on handoff */
 	reset_deassert_peripherals_handoff();
 
diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds
index 7199de4..81d954f 100644
--- a/arch/arm/cpu/ixp/u-boot.lds
+++ b/arch/arm/cpu/ixp/u-boot.lds
@@ -46,9 +46,11 @@ SECTIONS
 	. = ALIGN(4);
 
 	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+	#include <u-boot.lst>
+	}
 
 	. = ALIGN(4);
 
diff --git a/arch/arm/cpu/lh7a40x/Makefile b/arch/arm/cpu/lh7a40x/Makefile
deleted file mode 100644
index 01cf7f5..0000000
--- a/arch/arm/cpu/lh7a40x/Makefile
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-COBJS	= cpu.o speed.o timer.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/lh7a40x/config.mk b/arch/arm/cpu/lh7a40x/config.mk
deleted file mode 100644
index 1c4aa97..0000000
--- a/arch/arm/cpu/lh7a40x/config.mk
+++ /dev/null
@@ -1,33 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
-PLATFORM_CPPFLAGS += -march=armv4
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# ========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
diff --git a/arch/arm/cpu/lh7a40x/cpu.c b/arch/arm/cpu/lh7a40x/cpu.c
deleted file mode 100644
index b193189..0000000
--- a/arch/arm/cpu/lh7a40x/cpu.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/system.h>
-
-static void cache_flush(void);
-
-int cleanup_before_linux (void)
-{
-	/*
-	 * this function is called just before we call linux
-	 * it prepares the processor for linux
-	 *
-	 * we turn off caches etc ...
-	 */
-
-	disable_interrupts ();
-
-	/* turn off I/D-cache */
-	icache_disable();
-	dcache_disable();
-
-	/* flush I/D-cache */
-	cache_flush();
-
-	return 0;
-}
-
-/* flush I/D-cache */
-static void cache_flush (void)
-{
-	unsigned long i = 0;
-
-	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
-}
diff --git a/arch/arm/cpu/lh7a40x/speed.c b/arch/arm/cpu/lh7a40x/speed.c
deleted file mode 100644
index 333ebb5..0000000
--- a/arch/arm/cpu/lh7a40x/speed.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <lh7a40x.h>
-
-
-/* ------------------------------------------------------------------------- */
-/* NOTE: This describes the proper use of this file.
- *
- * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
- *
- * get_FCLK(), get_HCLK(), get_PCLK() return the clock of
- * the specified bus in HZ.
- */
-/* ------------------------------------------------------------------------- */
-
-ulong get_PLLCLK (void)
-{
-	return CONFIG_SYS_CLK_FREQ;
-}
-
-/* return FCLK frequency */
-ulong get_FCLK (void)
-{
-	lh7a40x_csc_t* csc = LH7A40X_CSC_PTR;
-	ulong maindiv1, maindiv2, prediv, ps;
-
-	/*
-	 * from userguide 6.1.1.2
-	 *
-	 * FCLK = ((MAINDIV1 +2) * (MAINDIV2 +2) * 14.7456MHz) /
-	 *                   ((PREDIV+2) * (2^PS))
-	 */
-	maindiv2 = (csc->clkset & CLKSET_MAINDIV2) >> 11;
-	maindiv1 = (csc->clkset & CLKSET_MAINDIV1) >> 7;
-	prediv = (csc->clkset & CLKSET_PREDIV) >> 2;
-	ps = (csc->clkset & CLKSET_PS) >> 16;
-
-	return (((maindiv2 + 2) * (maindiv1 + 2) * CONFIG_SYS_CLK_FREQ) /
-		((prediv + 2) * (1 << ps)));
-}
-
-
-/* return HCLK frequency */
-ulong get_HCLK (void)
-{
-	lh7a40x_csc_t* csc = LH7A40X_CSC_PTR;
-
-	return (get_FCLK () / ((csc->clkset & CLKSET_HCLKDIV) + 1));
-}
-
-/* return PCLK frequency */
-ulong get_PCLK (void)
-{
-	lh7a40x_csc_t* csc = LH7A40X_CSC_PTR;
-
-	return (get_HCLK () /
-		(1 << (((csc->clkset & CLKSET_PCLKDIV) >> 16) + 1)));
-}
diff --git a/arch/arm/cpu/lh7a40x/start.S b/arch/arm/cpu/lh7a40x/start.S
deleted file mode 100644
index 33b9269..0000000
--- a/arch/arm/cpu/lh7a40x/start.S
+++ /dev/null
@@ -1,506 +0,0 @@
-/*
- *  armboot - Startup Code for ARM920 CPU-core
- *
- *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
- *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
- *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-
-/*
- *************************************************************************
- *
- * Jump vector table as in table 3.1 in [1]
- *
- *************************************************************************
- */
-
-
-.globl _start
-_start:	b       reset
-	ldr	pc, _undefined_instruction
-	ldr	pc, _software_interrupt
-	ldr	pc, _prefetch_abort
-	ldr	pc, _data_abort
-	ldr	pc, _not_used
-	ldr	pc, _irq
-	ldr	pc, _fiq
-
-_undefined_instruction:	.word undefined_instruction
-_software_interrupt:	.word software_interrupt
-_prefetch_abort:	.word prefetch_abort
-_data_abort:		.word data_abort
-_not_used:		.word not_used
-_irq:			.word irq
-_fiq:			.word fiq
-
-	.balignl 16,0xdeadbeef
-
-
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * relocate armboot to ram
- * setup stack
- * jump to second stage
- *
- *************************************************************************
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end__ - _start
-
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-	.word	0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-	.word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
-	.word	0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0xd3
-	msr	cpsr,r0
-
-#define pWDTCTL		0x80001400  /* Watchdog Timer control register */
-#define pINTENC		0x8000050C  /* Interrupt-Controller enable clear register */
-#define pCLKSET		0x80000420  /* clock divisor register */
-
-	/* disable watchdog, set watchdog control register to
-	 * all zeros (default reset)
-	 */
-	ldr     r0, =pWDTCTL
-	mov     r1, #0x0
-	str     r1, [r0]
-
-	/*
-	 * mask all IRQs by setting all bits in the INTENC register (default)
-	 */
-	mov	r1, #0xffffffff
-	ldr	r0, =pINTENC
-	str	r1, [r0]
-
-	/* FCLK:HCLK:PCLK = 1:2:2 */
-	/* default FCLK is 200 MHz, using 14.7456 MHz fin */
-	ldr	r0, =pCLKSET
-	ldr r1, =0x0004ee39
-@	ldr r1, =0x0005ee39	@ 1: 2: 4
-	str	r1, [r0]
-
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl	cpu_init_crit
-#endif
-
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
-	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
-	ldr	r0,=0x00000000
-	bl	board_init_f
-
-/*------------------------------------------------------------------------------*/
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- */
-	.globl	relocate_code
-relocate_code:
-	mov	r4, r0	/* save addr_sp */
-	mov	r5, r1	/* save addr of gd */
-	mov	r6, r2	/* save addr of destination */
-
-	/* Set up the stack						    */
-stack_setup:
-	mov	sp, r4
-
-	adr	r0, _start
-	cmp	r0, r6
-	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
-	beq	clear_bss		/* skip relocation */
-	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _bss_start_ofs
-	add	r2, r0, r3		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-	/*
-	 * fix .rel.dyn relocations
-	 */
-	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
-	sub	r9, r6, r0		/* r9 <- relocation offset */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
-	add	r10, r10, r0		/* r10 <- sym table in FLASH */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
-	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
-	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
-fixloop:
-	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23			/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2			/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
-	/* relative fix: increase location by offset */
-	ldr	r1, [r0]
-	add	r1, r1, r9
-fixnext:
-	str	r1, [r0]
-	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
-	cmp	r2, r3
-	blo	fixloop
-#endif
-
-clear_bss:
-#ifndef CONFIG_SPL_BUILD
-	ldr	r0, _bss_start_ofs
-	ldr	r1, _bss_end_ofs
-	mov	r4, r6			/* reloc addr */
-	add	r0, r0, r4
-	add	r1, r1, r4
-	mov	r2, #0x00000000		/* clear			    */
-
-clbss_l:cmp	r0, r1			/* clear loop... */
-	bhs	clbss_e			/* if reached end of bss, exit */
-	str	r2, [r0]
-	add	r0, r0, #4
-	b	clbss_l
-clbss_e:
-#endif
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-	ldr	r0, _board_init_r_ofs
-	adr	r1, _start
-	add	lr, r0, r1
-	add	lr, lr, r9
-	/* setup parameters for board_init_r */
-	mov	r0, r5		/* gd_t */
-	mov	r1, r6		/* dest_addr */
-	/* jump to it ... */
-	mov	pc, lr
-
-_board_init_r_ofs:
-	.word board_init_r - _start
-
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-
-
-cpu_init_crit:
-	/*
-	 * flush v4 I/D caches
-	 */
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
-	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
-
-	/*
-	 * disable MMU stuff and caches
-	 */
-	mrc	p15, 0, r0, c1, c0, 0
-	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
-	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
-	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
-	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
-	orr	r0, r0, #0x40000000	@ set bit 30 (nF) notFastBus
-	mcr	p15, 0, r0, c1, c0, 0
-
-
-	/*
-	 * before relocating, we have to setup RAM timing
-	 * because memory timing is board-dependend, you will
-	 * find a lowlevel_init.S in your board directory.
-	 */
-	mov	ip, lr
-	bl	lowlevel_init
-	mov	lr, ip
-
-	mov	pc, lr
-
-
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE	72
-
-#define S_OLD_R0	68
-#define S_PSR		64
-#define S_PC		60
-#define S_LR		56
-#define S_SP		52
-
-#define S_IP		48
-#define S_FP		44
-#define S_R10		40
-#define S_R9		36
-#define S_R8		32
-#define S_R7		28
-#define S_R6		24
-#define S_R5		20
-#define S_R4		16
-#define S_R3		12
-#define S_R2		8
-#define S_R1		4
-#define S_R0		0
-
-#define MODE_SVC 0x13
-#define I_BIT	 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
-	.macro	bad_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	ldr	r2, IRQ_STACK_START_IN
-	ldmia	r2, {r2 - r3}			@ get pc, cpsr
-	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
-
-	add	r5, sp, #S_SP
-	mov	r1, lr
-	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
-	mov	r0, sp
-	.endm
-
-	.macro	irq_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	add     r8, sp, #S_PC
-	stmdb   r8, {sp, lr}^                   @ Calling SP, LR
-	str     lr, [r8, #0]                    @ Save calling PC
-	mrs     r6, spsr
-	str     r6, [r8, #4]                    @ Save CPSR
-	str     r0, [r8, #8]                    @ Save OLD_R0
-	mov	r0, sp
-	.endm
-
-	.macro	irq_restore_user_regs
-	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
-	mov	r0, r0
-	ldr	lr, [sp, #S_PC]			@ Get PC
-	add	sp, sp, #S_FRAME_SIZE
-	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
-	.endm
-
-	.macro get_bad_stack
-	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
-
-	str	lr, [r13]			@ save caller lr / spsr
-	mrs	lr, spsr
-	str     lr, [r13, #4]
-
-	mov	r13, #MODE_SVC			@ prepare SVC-Mode
-	@ msr	spsr_c, r13
-	msr	spsr, r13
-	mov	lr, pc
-	movs	pc, lr
-	.endm
-
-	.macro get_irq_stack			@ setup IRQ stack
-	ldr	sp, IRQ_STACK_START
-	.endm
-
-	.macro get_fiq_stack			@ setup FIQ stack
-	ldr	sp, FIQ_STACK_START
-	.endm
-
-/*
- * exception handlers
- */
-	.align  5
-undefined_instruction:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_undefined_instruction
-
-	.align	5
-software_interrupt:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_software_interrupt
-
-	.align	5
-prefetch_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_prefetch_abort
-
-	.align	5
-data_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_data_abort
-
-	.align	5
-not_used:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
-	.align	5
-irq:
-	get_irq_stack
-	irq_save_user_regs
-	bl	do_irq
-	irq_restore_user_regs
-
-	.align	5
-fiq:
-	get_fiq_stack
-	/* someone ought to write a more effiction fiq_save_user_regs */
-	irq_save_user_regs
-	bl	do_fiq
-	irq_restore_user_regs
-
-#else
-
-	.align	5
-irq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_irq
-
-	.align	5
-fiq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_fiq
-
-#endif
-
-	.align	5
-.globl reset_cpu
-reset_cpu:
-	bl	disable_interrupts
-
-	/* Disable watchdog */
-	ldr	r1, =pWDTCTL
-	mov	r3, #0
-	str	r3, [r1]
-
-	/* reset counter */
-	ldr	r3, =0x00001984
-	str	r3, [r1, #4]
-
-	/* Enable the watchdog */
-	mov	r3, #1
-	str	r3, [r1]
-
-_loop_forever:
-	b	_loop_forever
diff --git a/arch/arm/cpu/lh7a40x/timer.c b/arch/arm/cpu/lh7a40x/timer.c
deleted file mode 100644
index 58b35b1..0000000
--- a/arch/arm/cpu/lh7a40x/timer.c
+++ /dev/null
@@ -1,182 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <lh7a40x.h>
-
-static ulong timer_load_val = 0;
-
-/* macro to read the 16 bit timer */
-static inline ulong READ_TIMER(void)
-{
-	lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR;
-	lh7a40x_timer_t* timer = &timers->timer1;
-
-	return (timer->value & 0x0000ffff);
-}
-
-static ulong timestamp;
-static ulong lastdec;
-
-int timer_init (void)
-{
-	lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR;
-	lh7a40x_timer_t* timer = &timers->timer1;
-
-	/* a periodic timer using the 508kHz source */
-	timer->control = (TIMER_PER | TIMER_CLK508K);
-
-	if (timer_load_val == 0) {
-		/*
-		 * 10ms period with 508.469kHz clock = 5084
-		 */
-		timer_load_val = CONFIG_SYS_HZ/100;
-	}
-
-	/* load value for 10 ms timeout */
-	lastdec = timer->load = timer_load_val;
-
-	/* auto load, start timer */
-	timer->control = timer->control | TIMER_EN;
-	timestamp = 0;
-
-	return (0);
-}
-
-/*
- * timer without interrupts
- */
-ulong get_timer (ulong base)
-{
-	return (get_timer_masked() - base);
-}
-
-void __udelay (unsigned long usec)
-{
-	ulong tmo,tmp;
-
-	/* normalize */
-	if (usec >= 1000) {
-		tmo = usec / 1000;
-		tmo *= CONFIG_SYS_HZ;
-		tmo /= 1000;
-	}
-	else {
-		if (usec > 1) {
-			tmo = usec * CONFIG_SYS_HZ;
-			tmo /= (1000*1000);
-		}
-		else
-			tmo = 1;
-	}
-
-	/* check for rollover during this delay */
-	tmp = get_timer (0);
-	if ((tmp + tmo) < tmp )
-		reset_timer_masked();  /* timer would roll over */
-	else
-		tmo += tmp;
-
-	while (get_timer_masked () < tmo);
-}
-
-void reset_timer_masked (void)
-{
-	/* reset time */
-	lastdec = READ_TIMER();
-	timestamp = 0;
-}
-
-ulong get_timer_masked (void)
-{
-	ulong now = READ_TIMER();
-
-	if (lastdec >= now) {
-		/* normal mode */
-		timestamp += (lastdec - now);
-	} else {
-		/* we have an overflow ... */
-		timestamp += ((lastdec + timer_load_val) - now);
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-void udelay_masked (unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	/* normalize */
-	if (usec >= 1000) {
-		tmo = usec / 1000;
-		tmo *= CONFIG_SYS_HZ;
-		tmo /= 1000;
-	} else {
-		if (usec > 1) {
-			tmo = usec * CONFIG_SYS_HZ;
-			tmo /= (1000*1000);
-		} else {
-			tmo = 1;
-		}
-	}
-
-	endtime = get_timer_masked () + tmo;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-	ulong tbclk;
-
-	tbclk = timer_load_val * 100;
-
-	return tbclk;
-}
diff --git a/arch/arm/cpu/tegra20-common/emc.c b/arch/arm/cpu/tegra20-common/emc.c
index 97420d7..90edf00 100644
--- a/arch/arm/cpu/tegra20-common/emc.c
+++ b/arch/arm/cpu/tegra20-common/emc.c
@@ -257,7 +257,7 @@ static int decode_emc(const void *blob, unsigned rate, struct emc_ctlr **emcp,
 int tegra_set_emc(const void *blob, unsigned rate)
 {
 	struct emc_ctlr *emc;
-	const u32 *table;
+	const u32 *table = NULL;
 	int err, i;
 
 	err = decode_emc(blob, rate, &emc, &table);
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index e49ca0c..e6b202b 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -34,8 +34,8 @@ SECTIONS
 	.text :
 	{
 		__image_copy_start = .;
-		CPUDIR/start.o (.text)
-		*(.text)
+		CPUDIR/start.o (.text*)
+		*(.text*)
 	}
 
 	. = ALIGN(4);
@@ -43,15 +43,17 @@ SECTIONS
 
 	. = ALIGN(4);
 	.data : {
-		*(.data)
+		*(.data*)
 	}
 
 	. = ALIGN(4);
 
 	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+	#include <u-boot.lst>
+	}
 
 	. = ALIGN(4);
 
@@ -81,7 +83,7 @@ SECTIONS
 
 	.bss __rel_dyn_start (OVERLAY) : {
 		__bss_start = .;
-		*(.bss)
+		*(.bss*)
 		 . = ALIGN(4);
 		__bss_end__ = .;
 	}
@@ -92,3 +94,7 @@ SECTIONS
 	/DISCARD/ : { *(.interp*) }
 	/DISCARD/ : { *(.gnu*) }
 }
+
+#if defined(CONFIG_SPL_TEXT_BASE) && defined(CONFIG_SPL_MAX_SIZE)
+ASSERT(__bss_end__ < (CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE), "SPL image too big");
+#endif
diff --git a/arch/arm/imx-common/cmd_bmode.c b/arch/arm/imx-common/cmd_bmode.c
index 02fe72e..ddc14b0 100644
--- a/arch/arm/imx-common/cmd_bmode.c
+++ b/arch/arm/imx-common/cmd_bmode.c
@@ -24,6 +24,7 @@
 #include <asm/io.h>
 #include <asm/imx-common/boot_mode.h>
 #include <malloc.h>
+#include <command.h>
 
 static const struct boot_mode *modes[2];
 
@@ -103,9 +104,11 @@ void add_board_boot_modes(const struct boot_mode *p)
 	int size;
 	char *dest;
 
-	if (__u_boot_cmd_bmode.usage) {
-		free(__u_boot_cmd_bmode.usage);
-		__u_boot_cmd_bmode.usage = NULL;
+	cmd_tbl_t *entry = ll_entry_get(cmd_tbl_t, bmode, cmd);
+
+	if (entry->usage) {
+		free(entry->usage);
+		entry->usage = NULL;
 	}
 
 	modes[0] = p;
@@ -114,6 +117,6 @@ void add_board_boot_modes(const struct boot_mode *p)
 	dest = malloc(size);
 	if (dest) {
 		create_usage(dest);
-		__u_boot_cmd_bmode.usage = dest;
+		entry->usage = dest;
 	}
 }
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 6cfbef7..819fd2f 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -169,6 +169,12 @@ struct cm_dpll {
 	unsigned int clktimer2clk;	/* offset 0x08 */
 };
 
+/* Control Module RTC registers */
+struct cm_rtc {
+	unsigned int rtcclkctrl;	/* offset 0x0 */
+	unsigned int clkstctrl;		/* offset 0x4 */
+};
+
 /* Watchdog timer registers */
 struct wd_timer {
 	unsigned int resv1[4];
@@ -218,6 +224,15 @@ struct gptimer {
 	unsigned int tcar2;		/* offset 0x58 */
 };
 
+/* RTC Registers */
+struct rtc_regs {
+	unsigned int res[21];
+	unsigned int osc;		/* offset 0x54 */
+	unsigned int res2[5];
+	unsigned int kick0r;		/* offset 0x6c */
+	unsigned int kick1r;		/* offset 0x70 */
+};
+
 /* UART Registers */
 struct uart_sys {
 	unsigned int resv1[21];
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 6b22c45..8e69fb6 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -29,40 +29,41 @@
 #define PHY_DLL_LOCK_DIFF	0x0
 #define DDR_CKE_CTRL_NORMAL	0x1
 
-#define DDR2_EMIF_READ_LATENCY	0x100005	/* Enable Dynamic Power Down */
-#define DDR2_EMIF_TIM1		0x0666B3C9
-#define DDR2_EMIF_TIM2		0x243631CA
-#define DDR2_EMIF_TIM3		0x0000033F
-#define DDR2_EMIF_SDCFG		0x41805332
-#define DDR2_EMIF_SDREF		0x0000081a
-#define DDR2_DLL_LOCK_DIFF	0x0
-#define DDR2_RATIO		0x80
-#define DDR2_INVERT_CLKOUT	0x00
-#define DDR2_RD_DQS		0x12
-#define DDR2_WR_DQS		0x00
-#define DDR2_PHY_WRLVL		0x00
-#define DDR2_PHY_GATELVL	0x00
-#define DDR2_PHY_WR_DATA	0x40
-#define DDR2_PHY_FIFO_WE	0x80
-#define DDR2_PHY_RANK0_DELAY	0x1
-#define DDR2_IOCTRL_VALUE	0x18B
+/* Micron MT47H128M16RT-25E */
+#define MT47H128M16RT25E_EMIF_READ_LATENCY	0x100005
+#define MT47H128M16RT25E_EMIF_TIM1		0x0666B3C9
+#define MT47H128M16RT25E_EMIF_TIM2		0x243631CA
+#define MT47H128M16RT25E_EMIF_TIM3		0x0000033F
+#define MT47H128M16RT25E_EMIF_SDCFG		0x41805332
+#define MT47H128M16RT25E_EMIF_SDREF		0x0000081a
+#define MT47H128M16RT25E_DLL_LOCK_DIFF		0x0
+#define MT47H128M16RT25E_RATIO			0x80
+#define MT47H128M16RT25E_INVERT_CLKOUT		0x00
+#define MT47H128M16RT25E_RD_DQS			0x12
+#define MT47H128M16RT25E_WR_DQS			0x00
+#define MT47H128M16RT25E_PHY_WRLVL		0x00
+#define MT47H128M16RT25E_PHY_GATELVL		0x00
+#define MT47H128M16RT25E_PHY_WR_DATA		0x40
+#define MT47H128M16RT25E_PHY_FIFO_WE		0x80
+#define MT47H128M16RT25E_PHY_RANK0_DELAY		0x1
+#define MT47H128M16RT25E_IOCTRL_VALUE		0x18B
 
 /* Micron MT41J128M16JT-125 */
-#define DDR3_EMIF_READ_LATENCY	0x06
-#define DDR3_EMIF_TIM1		0x0888A39B
-#define DDR3_EMIF_TIM2		0x26337FDA
-#define DDR3_EMIF_TIM3		0x501F830F
-#define DDR3_EMIF_SDCFG		0x61C04AB2
-#define DDR3_EMIF_SDREF		0x0000093B
-#define DDR3_ZQ_CFG		0x50074BE4
-#define DDR3_DLL_LOCK_DIFF	0x1
-#define DDR3_RATIO		0x40
-#define DDR3_INVERT_CLKOUT	0x1
-#define DDR3_RD_DQS		0x3B
-#define DDR3_WR_DQS		0x85
-#define DDR3_PHY_WR_DATA	0xC1
-#define DDR3_PHY_FIFO_WE	0x100
-#define DDR3_IOCTRL_VALUE	0x18B
+#define MT41J128MJT125_EMIF_READ_LATENCY	0x06
+#define MT41J128MJT125_EMIF_TIM1		0x0888A39B
+#define MT41J128MJT125_EMIF_TIM2		0x26337FDA
+#define MT41J128MJT125_EMIF_TIM3		0x501F830F
+#define MT41J128MJT125_EMIF_SDCFG		0x61C04AB2
+#define MT41J128MJT125_EMIF_SDREF		0x0000093B
+#define MT41J128MJT125_ZQ_CFG			0x50074BE4
+#define MT41J128MJT125_DLL_LOCK_DIFF		0x1
+#define MT41J128MJT125_RATIO			0x40
+#define MT41J128MJT125_INVERT_CLKOUT		0x1
+#define MT41J128MJT125_RD_DQS			0x3B
+#define MT41J128MJT125_WR_DQS			0x85
+#define MT41J128MJT125_PHY_WR_DATA		0xC1
+#define MT41J128MJT125_PHY_FIFO_WE		0x100
+#define MT41J128MJT125_IOCTRL_VALUE		0x18B
 
 /**
  * Configure SDRAM
@@ -189,6 +190,8 @@ struct ddr_ctrl {
 	unsigned int ddrckectrl;
 };
 
-void config_ddr(short ddr_type);
+void config_ddr(unsigned int pll, unsigned int ioctrl,
+		const struct ddr_data *data, const struct cmd_control *ctrl,
+		const struct emif_regs *regs);
 
 #endif  /* _DDR_DEFS_H */
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
index 62332f2..5bd4bc8 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -61,6 +61,7 @@
 #define CM_WKUP				0x44E00400
 #define CM_DPLL				0x44E00500
 #define CM_DEVICE			0x44E00700
+#define CM_RTC				0x44E00800
 #define CM_CEFUSE			0x44E00A00
 #define PRM_DEVICE			0x44E00F00
 
@@ -83,4 +84,7 @@
 #define AM335X_CPSW_BASE		0x4A100000
 #define AM335X_CPSW_MDIO_BASE		0x4A101000
 
+/* RTC base address */
+#define AM335X_RTC_BASE			0x44E3E000
+
 #endif /* __AM33XX_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h
new file mode 100644
index 0000000..aed6b00
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/mux.h
@@ -0,0 +1,261 @@
+/*
+ * mux.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MUX_H_
+#define _MUX_H_
+
+#include <common.h>
+#include <asm/io.h>
+
+#define MUX_CFG(value, offset)	\
+	__raw_writel(value, (CTRL_BASE + offset));
+
+/* PAD Control Fields */
+#define SLEWCTRL	(0x1 << 6)
+#define RXACTIVE	(0x1 << 5)
+#define PULLUP_EN	(0x1 << 4) /* Pull UP Selection */
+#define PULLUDEN	(0x0 << 3) /* Pull up enabled */
+#define PULLUDDIS	(0x1 << 3) /* Pull up disabled */
+#define MODE(val)	val	/* used for Readability */
+
+/*
+ * PAD CONTROL OFFSETS
+ * Field names corresponds to the pad signal name
+ */
+struct pad_signals {
+	int gpmc_ad0;
+	int gpmc_ad1;
+	int gpmc_ad2;
+	int gpmc_ad3;
+	int gpmc_ad4;
+	int gpmc_ad5;
+	int gpmc_ad6;
+	int gpmc_ad7;
+	int gpmc_ad8;
+	int gpmc_ad9;
+	int gpmc_ad10;
+	int gpmc_ad11;
+	int gpmc_ad12;
+	int gpmc_ad13;
+	int gpmc_ad14;
+	int gpmc_ad15;
+	int gpmc_a0;
+	int gpmc_a1;
+	int gpmc_a2;
+	int gpmc_a3;
+	int gpmc_a4;
+	int gpmc_a5;
+	int gpmc_a6;
+	int gpmc_a7;
+	int gpmc_a8;
+	int gpmc_a9;
+	int gpmc_a10;
+	int gpmc_a11;
+	int gpmc_wait0;
+	int gpmc_wpn;
+	int gpmc_be1n;
+	int gpmc_csn0;
+	int gpmc_csn1;
+	int gpmc_csn2;
+	int gpmc_csn3;
+	int gpmc_clk;
+	int gpmc_advn_ale;
+	int gpmc_oen_ren;
+	int gpmc_wen;
+	int gpmc_be0n_cle;
+	int lcd_data0;
+	int lcd_data1;
+	int lcd_data2;
+	int lcd_data3;
+	int lcd_data4;
+	int lcd_data5;
+	int lcd_data6;
+	int lcd_data7;
+	int lcd_data8;
+	int lcd_data9;
+	int lcd_data10;
+	int lcd_data11;
+	int lcd_data12;
+	int lcd_data13;
+	int lcd_data14;
+	int lcd_data15;
+	int lcd_vsync;
+	int lcd_hsync;
+	int lcd_pclk;
+	int lcd_ac_bias_en;
+	int mmc0_dat3;
+	int mmc0_dat2;
+	int mmc0_dat1;
+	int mmc0_dat0;
+	int mmc0_clk;
+	int mmc0_cmd;
+	int mii1_col;
+	int mii1_crs;
+	int mii1_rxerr;
+	int mii1_txen;
+	int mii1_rxdv;
+	int mii1_txd3;
+	int mii1_txd2;
+	int mii1_txd1;
+	int mii1_txd0;
+	int mii1_txclk;
+	int mii1_rxclk;
+	int mii1_rxd3;
+	int mii1_rxd2;
+	int mii1_rxd1;
+	int mii1_rxd0;
+	int rmii1_refclk;
+	int mdio_data;
+	int mdio_clk;
+	int spi0_sclk;
+	int spi0_d0;
+	int spi0_d1;
+	int spi0_cs0;
+	int spi0_cs1;
+	int ecap0_in_pwm0_out;
+	int uart0_ctsn;
+	int uart0_rtsn;
+	int uart0_rxd;
+	int uart0_txd;
+	int uart1_ctsn;
+	int uart1_rtsn;
+	int uart1_rxd;
+	int uart1_txd;
+	int i2c0_sda;
+	int i2c0_scl;
+	int mcasp0_aclkx;
+	int mcasp0_fsx;
+	int mcasp0_axr0;
+	int mcasp0_ahclkr;
+	int mcasp0_aclkr;
+	int mcasp0_fsr;
+	int mcasp0_axr1;
+	int mcasp0_ahclkx;
+	int xdma_event_intr0;
+	int xdma_event_intr1;
+	int nresetin_out;
+	int porz;
+	int nnmi;
+	int osc0_in;
+	int osc0_out;
+	int rsvd1;
+	int tms;
+	int tdi;
+	int tdo;
+	int tck;
+	int ntrst;
+	int emu0;
+	int emu1;
+	int osc1_in;
+	int osc1_out;
+	int pmic_power_en;
+	int rtc_porz;
+	int rsvd2;
+	int ext_wakeup;
+	int enz_kaldo_1p8v;
+	int usb0_dm;
+	int usb0_dp;
+	int usb0_ce;
+	int usb0_id;
+	int usb0_vbus;
+	int usb0_drvvbus;
+	int usb1_dm;
+	int usb1_dp;
+	int usb1_ce;
+	int usb1_id;
+	int usb1_vbus;
+	int usb1_drvvbus;
+	int ddr_resetn;
+	int ddr_csn0;
+	int ddr_cke;
+	int ddr_ck;
+	int ddr_nck;
+	int ddr_casn;
+	int ddr_rasn;
+	int ddr_wen;
+	int ddr_ba0;
+	int ddr_ba1;
+	int ddr_ba2;
+	int ddr_a0;
+	int ddr_a1;
+	int ddr_a2;
+	int ddr_a3;
+	int ddr_a4;
+	int ddr_a5;
+	int ddr_a6;
+	int ddr_a7;
+	int ddr_a8;
+	int ddr_a9;
+	int ddr_a10;
+	int ddr_a11;
+	int ddr_a12;
+	int ddr_a13;
+	int ddr_a14;
+	int ddr_a15;
+	int ddr_odt;
+	int ddr_d0;
+	int ddr_d1;
+	int ddr_d2;
+	int ddr_d3;
+	int ddr_d4;
+	int ddr_d5;
+	int ddr_d6;
+	int ddr_d7;
+	int ddr_d8;
+	int ddr_d9;
+	int ddr_d10;
+	int ddr_d11;
+	int ddr_d12;
+	int ddr_d13;
+	int ddr_d14;
+	int ddr_d15;
+	int ddr_dqm0;
+	int ddr_dqm1;
+	int ddr_dqs0;
+	int ddr_dqsn0;
+	int ddr_dqs1;
+	int ddr_dqsn1;
+	int ddr_vref;
+	int ddr_vtp;
+	int ddr_strben0;
+	int ddr_strben1;
+	int ain7;
+	int ain6;
+	int ain5;
+	int ain4;
+	int ain3;
+	int ain2;
+	int ain1;
+	int ain0;
+	int vrefp;
+	int vrefn;
+};
+
+struct module_pin_mux {
+	short reg_offset;
+	unsigned char val;
+};
+
+/* Pad control register offset */
+#define PAD_CTRL_BASE	0x800
+#define OFFSET(x)	(unsigned int) (&((struct pad_signals *) \
+				(PAD_CTRL_BASE))->x)
+
+/*
+ * Configure the pin mux for the module
+ */
+void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux);
+
+#endif
diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h
index 63ed10b..644ff35 100644
--- a/arch/arm/include/asm/arch-am33xx/spl.h
+++ b/arch/arm/include/asm/arch-am33xx/spl.h
@@ -27,6 +27,7 @@
 #define BOOT_DEVICE_NAND	5
 #define BOOT_DEVICE_MMC1	8
 #define BOOT_DEVICE_MMC2	9	/* eMMC or daughter card */
+#define BOOT_DEVICE_SPI		11
 #define BOOT_DEVICE_UART	65
 #define BOOT_DEVICE_CPGMAC	70
 #define BOOT_DEVICE_MMC2_2      0xFF
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index 819ea65..9cf35e0 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -19,24 +19,6 @@
 #ifndef _SYS_PROTO_H_
 #define _SYS_PROTO_H_
 
-/*
- * AM335x parts define a system EEPROM that defines certain sub-fields.
- * We use these fields to in turn see what board we are on, and what
- * that might require us to set or not set.
- */
-#define HDR_NO_OF_MAC_ADDR	3
-#define HDR_ETH_ALEN		6
-#define HDR_NAME_LEN		8
-
-struct am335x_baseboard_id {
-	unsigned int  magic;
-	char name[HDR_NAME_LEN];
-	char version[4];
-	char serial[12];
-	char config[32];
-	char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
-};
-
 #define BOARD_REV_ID	0x0
 
 u32 get_cpu_rev(void);
@@ -51,13 +33,4 @@ u32 get_device_type(void);
 void setup_clocks_for_console(void);
 void ddr_pll_config(unsigned int ddrpll_M);
 
-/*
- * We have three pin mux functions that must exist.  We must be able to enable
- * uart0, for initial output and i2c0 to read the main EEPROM.  We then have a
- * main pinmux function that can be overridden to enable all other pinmux that
- * is required on the board.
- */
-void enable_uart0_pin_mux(void);
-void enable_i2c0_pin_mux(void);
-void enable_board_pin_mux(struct am335x_baseboard_id *header);
 #endif
diff --git a/arch/arm/include/asm/arch-arm720t/hardware.h b/arch/arm/include/asm/arch-arm720t/hardware.h
index 0a357b1..0a76610 100644
--- a/arch/arm/include/asm/arch-arm720t/hardware.h
+++ b/arch/arm/include/asm/arch-arm720t/hardware.h
@@ -24,9 +24,7 @@
  * MA 02111-1307 USA
  */
 
-#if defined(CONFIG_NETARM)
-#include <asm/arch-arm720t/netarm_registers.h>
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
 /* include IntegratorCP/CM720T specific hardware file if there was one */
 #else
 #error No hardware file defined for this configuration
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_dma_module.h b/arch/arm/include/asm/arch-arm720t/netarm_dma_module.h
deleted file mode 100644
index 328eaf0..0000000
--- a/arch/arm/include/asm/arch-arm720t/netarm_dma_module.h
+++ /dev/null
@@ -1,182 +0,0 @@
-/* * include/asm-armnommu/arch-netarm/netarm_dma_module.h
- *
- * Copyright (C) 2000 NETsilicon, Inc.
- * Copyright (C) 2000 WireSpeed Communications Corporation
- *
- * This software is copyrighted by WireSpeed. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall WireSpeed
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : Joe deBlaquiere
- *             David Smith
- */
-
-#ifndef __NETARM_DMA_MODULE_REGISTERS_H
-#define __NETARM_DMA_MODULE_REGISTERS_H
-
-/* GEN unit register offsets */
-
-#define	NETARM_DMA_MODULE_BASE		(0xFF900000)
-
-#define get_dma_reg_addr(c) ((volatile unsigned int *)(NETARM_DMA_MODULE_BASE + (c)))
-
-#define	NETARM_DMA1A_BFR_DESCRPTOR_PTR	(0x00)
-#define	NETARM_DMA1A_CONTROL		(0x10)
-#define	NETARM_DMA1A_STATUS		(0x14)
-#define	NETARM_DMA1B_BFR_DESCRPTOR_PTR	(0x20)
-#define	NETARM_DMA1B_CONTROL		(0x30)
-#define	NETARM_DMA1B_STATUS		(0x34)
-#define	NETARM_DMA1C_BFR_DESCRPTOR_PTR	(0x40)
-#define	NETARM_DMA1C_CONTROL		(0x50)
-#define	NETARM_DMA1C_STATUS		(0x54)
-#define	NETARM_DMA1D_BFR_DESCRPTOR_PTR	(0x60)
-#define	NETARM_DMA1D_CONTROL		(0x70)
-#define	NETARM_DMA1D_STATUS		(0x74)
-
-#define	NETARM_DMA2_BFR_DESCRPTOR_PTR	(0x80)
-#define	NETARM_DMA2_CONTROL		(0x90)
-#define	NETARM_DMA2_STATUS		(0x94)
-
-#define	NETARM_DMA3_BFR_DESCRPTOR_PTR	(0xA0)
-#define	NETARM_DMA3_CONTROL		(0xB0)
-#define	NETARM_DMA3_STATUS		(0xB4)
-
-#define	NETARM_DMA4_BFR_DESCRPTOR_PTR	(0xC0)
-#define	NETARM_DMA4_CONTROL		(0xD0)
-#define	NETARM_DMA4_STATUS		(0xD4)
-
-#define	NETARM_DMA5_BFR_DESCRPTOR_PTR	(0xE0)
-#define	NETARM_DMA5_CONTROL		(0xF0)
-#define	NETARM_DMA5_STATUS		(0xF4)
-
-#define	NETARM_DMA6_BFR_DESCRPTOR_PTR	(0x100)
-#define	NETARM_DMA6_CONTROL		(0x110)
-#define	NETARM_DMA6_STATUS		(0x114)
-
-#define	NETARM_DMA7_BFR_DESCRPTOR_PTR	(0x120)
-#define	NETARM_DMA7_CONTROL		(0x130)
-#define	NETARM_DMA7_STATUS		(0x134)
-
-#define	NETARM_DMA8_BFR_DESCRPTOR_PTR	(0x140)
-#define	NETARM_DMA8_CONTROL		(0x150)
-#define	NETARM_DMA8_STATUS		(0x154)
-
-#define	NETARM_DMA9_BFR_DESCRPTOR_PTR	(0x160)
-#define	NETARM_DMA9_CONTROL		(0x170)
-#define	NETARM_DMA9_STATUS		(0x174)
-
-#define	NETARM_DMA10_BFR_DESCRPTOR_PTR	(0x180)
-#define	NETARM_DMA10_CONTROL		(0x190)
-#define	NETARM_DMA10_STATUS		(0x194)
-
-/* select bitfield defintions */
-
-/* DMA Control Register ( 0xFF90_0XX0 ) */
-
-#define NETARM_DMA_CTL_ENABLE		(0x80000000)
-
-#define NETARM_DMA_CTL_ABORT		(0x40000000)
-
-#define NETARM_DMA_CTL_BUS_100_PERCENT	(0x00000000)
-#define NETARM_DMA_CTL_BUS_75_PERCENT	(0x10000000)
-#define NETARM_DMA_CTL_BUS_50_PERCENT	(0x20000000)
-#define NETARM_DMA_CTL_BUS_25_PERCENT	(0x30000000)
-
-#define NETARM_DMA_CTL_BUS_MASK		(0x30000000)
-
-#define NETARM_DMA_CTL_MODE_FB_TO_MEM	(0x00000000)
-#define NETARM_DMA_CTL_MODE_FB_FROM_MEM	(0x04000000)
-#define NETARM_DMA_CTL_MODE_MEM_TO_MEM	(0x08000000)
-
-#define NETARM_DMA_CTL_BURST_NONE	(0x00000000)
-#define NETARM_DMA_CTL_BURST_8_BYTE	(0x01000000)
-#define NETARM_DMA_CTL_BURST_16_BYTE	(0x02000000)
-
-#define NETARM_DMA_CTL_BURST_MASK	(0x03000000)
-
-#define NETARM_DMA_CTL_SRC_INCREMENT	(0x00200000)
-
-#define NETARM_DMA_CTL_DST_INCREMENT	(0x00100000)
-
-/* these apply only to ext xfers on DMA 3 or 4 */
-
-#define NETARM_DMA_CTL_CH_3_4_REQ_EXT	(0x00800000)
-
-#define NETARM_DMA_CTL_CH_3_4_DATA_32	(0x00000000)
-#define NETARM_DMA_CTL_CH_3_4_DATA_16	(0x00010000)
-#define NETARM_DMA_CTL_CH_3_4_DATA_8	(0x00020000)
-
-#define NETARM_DMA_CTL_STATE(X)	((X) & 0xFC00)
-#define NETARM_DMA_CTL_INDEX(X)	((X) & 0x03FF)
-
-/* DMA Status Register ( 0xFF90_0XX4 ) */
-
-#define NETARM_DMA_STAT_NC_INTPEN	(0x80000000)
-#define NETARM_DMA_STAT_EC_INTPEN	(0x40000000)
-#define NETARM_DMA_STAT_NR_INTPEN	(0x20000000)
-#define NETARM_DMA_STAT_CA_INTPEN	(0x10000000)
-#define NETARM_DMA_STAT_INTPEN_MASK	(0xF0000000)
-
-#define NETARM_DMA_STAT_NC_INT_EN	(0x00800000)
-#define NETARM_DMA_STAT_EC_INT_EN	(0x00400000)
-#define NETARM_DMA_STAT_NR_INT_EN	(0x00200000)
-#define NETARM_DMA_STAT_CA_INT_EN	(0x00100000)
-#define NETARM_DMA_STAT_INT_EN_MASK	(0x00F00000)
-
-#define NETARM_DMA_STAT_WRAP		(0x00080000)
-#define NETARM_DMA_STAT_IDONE		(0x00040000)
-#define NETARM_DMA_STAT_LAST		(0x00020000)
-#define NETARM_DMA_STAT_FULL		(0x00010000)
-
-#define	NETARM_DMA_STAT_BUFLEN(X)	((X) & 0x7FFF)
-
-/* DMA Buffer Descriptor Word 0 bitfields. */
-
-#define NETARM_DMA_BD0_WRAP		(0x80000000)
-#define NETARM_DMA_BD0_IDONE		(0x40000000)
-#define NETARM_DMA_BD0_LAST		(0x20000000)
-#define NETARM_DMA_BD0_BUFPTR_MASK	(0x1FFFFFFF)
-
-/* DMA Buffer Descriptor Word 1 bitfields. */
-
-#define NETARM_DMA_BD1_STATUS_MASK	(0xFFFF0000)
-#define NETARM_DMA_BD1_FULL		(0x00008000)
-#define NETARM_DMA_BD1_BUFLEN_MASK	(0x00007FFF)
-
-#ifndef	__ASSEMBLER__
-
-typedef	struct __NETARM_DMA_Buff_Desc_FlyBy
-{
-	unsigned int word0;
-	unsigned int word1;
-} NETARM_DMA_Buff_Desc_FlyBy, *pNETARM_DMA_Buff_Desc_FlyBy ;
-
-typedef	struct __NETARM_DMA_Buff_Desc_M_to_M
-{
-	unsigned int word0;
-	unsigned int word1;
-	unsigned int word2;
-	unsigned int word3;
-} NETARM_DMA_Buff_Desc_M_to_M, *pNETARM_DMA_Buff_Desc_M_to_M ;
-
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_eni_module.h b/arch/arm/include/asm/arch-arm720t/netarm_eni_module.h
deleted file mode 100644
index 317b354..0000000
--- a/arch/arm/include/asm/arch-arm720t/netarm_eni_module.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * include/asm-armnommu/arch-netarm/netarm_eni_module.h
- *
- * Copyright (C) 2000 NETsilicon, Inc.
- * Copyright (C) 2000 WireSpeed Communications Corporation
- *
- * This software is copyrighted by WireSpeed. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall WireSpeed
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : David Smith
- */
-
-#ifndef __NETARM_ENI_MODULE_REGISTERS_H
-#define __NETARM_ENI_MODULE_REGISTERS_H
-
-/* ENI unit register offsets */
-
-/* #ifdef CONFIG_ARCH_NETARM */
-#define	NETARM_ENI_MODULE_BASE		(0xFFA00000)
-/* #endif / * CONFIG_ARCH_NETARM */
-
-#define get_eni_reg_addr(c) ((volatile unsigned int *)(NETARM_ENI_MODULE_BASE + (c)))
-#define get_eni_ctl_reg_addr(minor) \
-	(get_eni_reg_addr(NETARM_ENI_1284_PORT1_CONTROL) + (minor))
-
-#define	NETARM_ENI_GENERAL_CONTROL	(0x00)
-#define	NETARM_ENI_STATUS_CONTROL	(0x04)
-#define	NETARM_ENI_FIFO_MODE_DATA	(0x08)
-
-#define	NETARM_ENI_1284_PORT1_CONTROL	(0x10)
-#define	NETARM_ENI_1284_PORT2_CONTROL	(0x14)
-#define	NETARM_ENI_1284_PORT3_CONTROL	(0x18)
-#define	NETARM_ENI_1284_PORT4_CONTROL	(0x1c)
-
-#define	NETARM_ENI_1284_CHANNEL1_DATA	(0x20)
-#define	NETARM_ENI_1284_CHANNEL2_DATA	(0x24)
-#define	NETARM_ENI_1284_CHANNEL3_DATA	(0x28)
-#define	NETARM_ENI_1284_CHANNEL4_DATA	(0x2c)
-
-#define	NETARM_ENI_ENI_CONTROL		(0x30)
-#define	NETARM_ENI_ENI_PULSED_INTR	(0x34)
-#define	NETARM_ENI_ENI_SHARED_RAM_ADDR	(0x38)
-#define	NETARM_ENI_ENI_SHARED		(0x3c)
-
-/* select bitfield defintions */
-
-/* General Control Register (0xFFA0_0000) */
-
-#define NETARM_ENI_GCR_ENIMODE_IEEE1284	(0x00000001)
-#define NETARM_ENI_GCR_ENIMODE_SHRAM16	(0x00000004)
-#define NETARM_ENI_GCR_ENIMODE_SHRAM8	(0x00000005)
-#define NETARM_ENI_GCR_ENIMODE_FIFO16	(0x00000006)
-#define NETARM_ENI_GCR_ENIMODE_FIFO8	(0x00000007)
-
-#define NETARM_ENI_GCR_ENIMODE_MASK	(0x00000007)
-
-/* IEEE 1284 Port Control Registers 1-4 (0xFFA0_0010, 0xFFA0_0014,
-   0xFFA0_0018, 0xFFA0_001c) */
-
-#define NETARM_ENI_1284PC_PORT_ENABLE	(0x80000000)
-#define NETARM_ENI_1284PC_DMA_ENABLE	(0x40000000)
-#define NETARM_ENI_1284PC_OBE_INT_EN	(0x20000000)
-#define NETARM_ENI_1284PC_ACK_INT_EN	(0x10000000)
-#define NETARM_ENI_1284PC_ECP_MODE	(0x08000000)
-#define NETARM_ENI_1284PC_LOOPBACK_MODE	(0x04000000)
-
-#define NETARM_ENI_1284PC_STROBE_TIME0	(0x00000000) /* 0.5 uS */
-#define NETARM_ENI_1284PC_STROBE_TIME1	(0x01000000) /* 1.0 uS */
-#define NETARM_ENI_1284PC_STROBE_TIME2	(0x02000000) /* 5.0 uS */
-#define NETARM_ENI_1284PC_STROBE_TIME3	(0x03000000) /* 10.0 uS */
-#define NETARM_ENI_1284PC_STROBE_MASK	(0x03000000)
-
-#define NETARM_ENI_1284PC_MAN_STROBE_EN	(0x00800000)
-#define NETARM_ENI_1284PC_FAST_MODE	(0x00400000)
-#define NETARM_ENI_1284PC_BIDIR_MODE	(0x00200000)
-
-#define NETARM_ENI_1284PC_MAN_STROBE	(0x00080000)
-#define NETARM_ENI_1284PC_AUTO_FEED	(0x00040000)
-#define NETARM_ENI_1284PC_INIT		(0x00020000)
-#define NETARM_ENI_1284PC_HSELECT	(0x00010000)
-#define NETARM_ENI_1284PC_FE_INT_EN	(0x00008000)
-#define NETARM_ENI_1284PC_EPP_MODE	(0x00004000)
-#define NETARM_ENI_1284PC_IBR_INT_EN	(0x00002000)
-#define NETARM_ENI_1284PC_IBR		(0x00001000)
-
-#define NETARM_ENI_1284PC_RXFDB_1BYTE	(0x00000400)
-#define NETARM_ENI_1284PC_RXFDB_2BYTE	(0x00000800)
-#define NETARM_ENI_1284PC_RXFDB_3BYTE	(0x00000c00)
-#define NETARM_ENI_1284PC_RXFDB_4BYTE	(0x00000000)
-
-#define NETARM_ENI_1284PC_RBCC		(0x00000200)
-#define NETARM_ENI_1284PC_RBCT		(0x00000100)
-#define NETARM_ENI_1284PC_ACK		(0x00000080)
-#define NETARM_ENI_1284PC_FIFO_E	(0x00000040)
-#define NETARM_ENI_1284PC_OBE		(0x00000020)
-#define NETARM_ENI_1284PC_ACK_INT	(0x00000010)
-#define NETARM_ENI_1284PC_BUSY		(0x00000008)
-#define NETARM_ENI_1284PC_PE		(0x00000004)
-#define NETARM_ENI_1284PC_PSELECT	(0x00000002)
-#define NETARM_ENI_1284PC_FAULT		(0x00000001)
-
-#endif /* __NETARM_ENI_MODULE_REGISTERS_H */
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_eth_module.h b/arch/arm/include/asm/arch-arm720t/netarm_eth_module.h
deleted file mode 100644
index 8f2f369..0000000
--- a/arch/arm/include/asm/arch-arm720t/netarm_eth_module.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * include/asm-armnommu/arch-netarm/netarm_eth_module.h
- *
- * Copyright (C) 2000 NETsilicon, Inc.
- * Copyright (C) 2000 WireSpeed Communications Corporation
- *
- * This software is copyrighted by WireSpeed. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall WireSpeed
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : Jackie Smith Cashion
- *             David Smith
- */
-
-#ifndef __NETARM_ETH_MODULE_REGISTERS_H
-#define __NETARM_ETH_MODULE_REGISTERS_H
-
-/* ETH unit register offsets */
-
-#define	NETARM_ETH_MODULE_BASE		(0xFF800000)
-
-#define get_eth_reg_addr(c) ((volatile unsigned int *)(NETARM_ETH_MODULE_BASE + (c)))
-
-#define NETARM_ETH_GEN_CTRL		(0x000) /* Ethernet Gen Control Reg */
-#define NETARM_ETH_GEN_STAT		(0x004) /* Ethernet Gen Status Reg */
-#define NETARM_ETH_FIFO_DAT1            (0x008) /* Fifo Data Reg 1 */
-#define NETARM_ETH_FIFO_DAT2            (0x00C) /* Fifo Data Reg 2 */
-#define NETARM_ETH_TX_STAT              (0x010) /* Transmit Status Reg */
-#define NETARM_ETH_RX_STAT              (0x014) /* Receive Status Reg */
-
-#define NETARM_ETH_MAC_CFG		(0x400) /* MAC Configuration Reg */
-#define NETARM_ETH_PCS_CFG		(0x408) /* PCS Configuration Reg */
-#define NETARM_ETH_STL_CFG		(0x410) /* STL Configuration Reg */
-#define NETARM_ETH_B2B_IPG_GAP_TMR	(0x440) /* Back-to-back IPG
-						   Gap Timer Reg */
-#define NETARM_ETH_NB2B_IPG_GAP_TMR	(0x444) /* Non Back-to-back
-						   IPG Gap Timer Reg */
-#define NETARM_ETH_MII_CMD		(0x540) /* MII (PHY) Command Reg */
-#define NETARM_ETH_MII_ADDR		(0x544) /* MII Address Reg */
-#define NETARM_ETH_MII_WRITE		(0x548) /* MII Write Data Reg */
-#define NETARM_ETH_MII_READ		(0x54C) /* MII Read Data Reg */
-#define NETARM_ETH_MII_IND		(0x550) /* MII Indicators Reg */
-#define NETARM_ETH_MIB_CRCEC		(0x580) /* (MIB) CRC Error Counter */
-#define NETARM_ETH_MIB_AEC		(0x584) /* Alignment Error Counter */
-#define NETARM_ETH_MIB_CEC		(0x588) /* Code Error Counter */
-#define NETARM_ETH_MIB_LFC		(0x58C) /* Long Frame Counter */
-#define NETARM_ETH_MIB_SFC		(0x590) /* Short Frame Counter */
-#define NETARM_ETH_MIB_LCC		(0x594) /* Late Collision Counter */
-#define NETARM_ETH_MIB_EDC		(0x598) /* Excessive Deferral
-						   Counter */
-#define NETARM_ETH_MIB_MCC		(0x59C) /* Maximum Collision Counter */
-#define NETARM_ETH_SAL_FILTER		(0x5C0) /* SAL Station Address
-						   Filter Reg */
-#define NETARM_ETH_SAL_STATION_ADDR_1	(0x5C4) /* SAL Station Address
-						   Reg */
-#define NETARM_ETH_SAL_STATION_ADDR_2	(0x5C8)
-#define NETARM_ETH_SAL_STATION_ADDR_3	(0x5CC)
-#define NETARM_ETH_SAL_HASH_TBL_1	(0x5D0) /* SAL Multicast Hash Table*/
-#define NETARM_ETH_SAL_HASH_TBL_2	(0x5D4)
-#define NETARM_ETH_SAL_HASH_TBL_3	(0x5D8)
-#define NETARM_ETH_SAL_HASH_TBL_4	(0x5DC)
-
-/* select bitfield defintions */
-
-/* Ethernet General Control Register (0xFF80_0000) */
-
-#define NETARM_ETH_GCR_ERX		(0x80000000) /* Enable Receive FIFO */
-#define NETARM_ETH_GCR_ERXDMA		(0x40000000) /* Enable Receive DMA */
-#define NETARM_ETH_GCR_ETX		(0x00800000) /* Enable Transmit FIFO */
-#define NETARM_ETH_GCR_ETXDMA		(0x00400000) /* Enable Transmit DMA */
-#define NETARM_ETH_GCR_ETXWM_50		(0x00100000) /* Transmit FIFO Water
-							Mark.  Start transmit
-							when FIFO is 50%
-							full. */
-#define NETARM_ETH_GCR_PNA		(0x00000400) /* pSOS pNA Buffer
-							Descriptor Format */
-
-/* Ethernet General Status Register (0xFF80_0004) */
-
-#define NETARM_ETH_GST_RXFDB            (0x30000000)
-#define NETARM_ETH_GST_RXREGR		(0x08000000) /* Receive Register
-							Ready */
-#define NETARM_ETH_GST_RXFIFOH		(0x04000000)
-#define NETARM_ETH_GST_RXBR		(0x02000000)
-#define NETARM_ETH_GST_RXSKIP		(0x01000000)
-
-#define NETARM_ETH_GST_TXBC             (0x00020000)
-
-
-/* Ethernet Transmit Status Register (0xFF80_0010) */
-
-#define NETARM_ETH_TXSTAT_TXOK          (0x00008000)
-
-
-/* Ethernet Receive Status Register (0xFF80_0014) */
-
-#define NETARM_ETH_RXSTAT_SIZE          (0xFFFF0000)
-#define NETARM_ETH_RXSTAT_RXOK          (0x00002000)
-
-
-/* PCS Configuration Register (0xFF80_0408) */
-
-#define NETARM_ETH_PCSC_NOCFR		(0x1) /* Disable Ciphering */
-#define NETARM_ETH_PCSC_ENJAB		(0x2) /* Enable Jabber Protection */
-#define NETARM_ETH_PCSC_CLKS_25M	(0x0) /* 25 MHz Clock Speed Select */
-#define NETARM_ETH_PCSC_CLKS_33M	(0x4) /* 33 MHz Clock Speed Select */
-
-/* STL Configuration Register (0xFF80_0410) */
-
-#define NETARM_ETH_STLC_RXEN		(0x2) /* Enable Packet Receiver */
-#define NETARM_ETH_STLC_AUTOZ		(0x4) /* Auto Zero Statistics */
-
-/* MAC Configuration Register (0xFF80_0400) */
-
-#define NETARM_ETH_MACC_HUGEN		(0x1) /* Enable Unlimited Transmit
-						 Frame Sizes */
-#define NETARM_ETH_MACC_PADEN		(0x4) /* Automatic Pad Fill Frames
-						 to 64 Bytes */
-#define NETARM_ETH_MACC_CRCEN		(0x8) /* Append CRC to Transmit
-						 Frames */
-
-/* MII (PHY) Command Register (0xFF80_0540) */
-
-#define NETARM_ETH_MIIC_RSTAT		(0x1) /* Single Scan for Read Data */
-
-/* MII Indicators Register (0xFF80_0550) */
-
-#define NETARM_ETH_MIII_BUSY		(0x1) /* MII I/F Busy with
-						 Read/Write */
-
-/* SAL Station Address Filter Register (0xFF80_05C0) */
-
-#define NETARM_ETH_SALF_PRO		(0x8) /* Enable Promiscuous Mode */
-#define NETARM_ETH_SALF_PRM		(0x4) /* Accept All Multicast
-						 Packets */
-#define NETARM_ETH_SALF_PRA		(0x2) /* Accept Mulitcast Packets
-						 using Hash Table */
-#define NETARM_ETH_SALF_BROAD		(0x1) /* Accept All Broadcast
-						 Packets */
-
-
-#endif /* __NETARM_GEN_MODULE_REGISTERS_H */
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_gen_module.h b/arch/arm/include/asm/arch-arm720t/netarm_gen_module.h
deleted file mode 100644
index 13656a3..0000000
--- a/arch/arm/include/asm/arch-arm720t/netarm_gen_module.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * include/asm-armnommu/arch-netarm/netarm_gen_module.h
- *
- * Copyright (C) 2005
- * Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
- *
- * Copyright (C) 2000, 2001 NETsilicon, Inc.
- * Copyright (C) 2000, 2001 Red Hat, Inc.
- *
- * This software is copyrighted by Red Hat. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall Red Hat
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : Joe deBlaquiere
- *
- * Modified to support NS7520 by Art Shipkowski.
- */
-
-#ifndef __NETARM_GEN_MODULE_REGISTERS_H
-#define __NETARM_GEN_MODULE_REGISTERS_H
-
-/* GEN unit register offsets */
-
-#define NETARM_GEN_MODULE_BASE		(0xFFB00000)
-
-#define get_gen_reg_addr(c) ((volatile unsigned int *)(NETARM_GEN_MODULE_BASE + (c)))
-
-#define NETARM_GEN_SYSTEM_CONTROL	(0x00)
-#define NETARM_GEN_STATUS_CONTROL	(0x04)
-#define NETARM_GEN_PLL_CONTROL		(0x08)
-#define NETARM_GEN_SOFTWARE_SERVICE	(0x0c)
-
-#define NETARM_GEN_TIMER1_CONTROL	(0x10)
-#define NETARM_GEN_TIMER1_STATUS	(0x14)
-#define NETARM_GEN_TIMER2_CONTROL	(0x18)
-#define NETARM_GEN_TIMER2_STATUS	(0x1c)
-
-#define NETARM_GEN_PORTA		(0x20)
-#ifndef CONFIG_NETARM_NS7520
-#define NETARM_GEN_PORTB		(0x24)
-#endif
-#define NETARM_GEN_PORTC		(0x28)
-
-#define NETARM_GEN_INTR_ENABLE		(0x30)
-#define NETARM_GEN_INTR_ENABLE_SET	(0x34)
-#define NETARM_GEN_INTR_ENABLE_CLR	(0x38)
-#define NETARM_GEN_INTR_STATUS_EN	(0x34)
-#define NETARM_GEN_INTR_STATUS_RAW	(0x38)
-
-#define NETARM_GEN_CACHE_CONTROL1	(0x40)
-#define NETARM_GEN_CACHE_CONTROL2	(0x44)
-
-/* select bitfield definitions */
-
-/* System Control Register ( 0xFFB0_0000 ) */
-
-#define NETARM_GEN_SYS_CFG_LENDIAN	(0x80000000)
-#define NETARM_GEN_SYS_CFG_BENDIAN	(0x00000000)
-
-#define NETARM_GEN_SYS_CFG_BUSQRTR	(0x00000000)
-#define NETARM_GEN_SYS_CFG_BUSHALF	(0x20000000)
-#define NETARM_GEN_SYS_CFG_BUSFULL	(0x40000000)
-
-#define NETARM_GEN_SYS_CFG_BCLK_DISABLE (0x10000000)
-
-#define NETARM_GEN_SYS_CFG_WDOG_EN	(0x01000000)
-#define NETARM_GEN_SYS_CFG_WDOG_IRQ	(0x00000000)
-#define NETARM_GEN_SYS_CFG_WDOG_FIQ	(0x00400000)
-#define NETARM_GEN_SYS_CFG_WDOG_RST	(0x00800000)
-#define NETARM_GEN_SYS_CFG_WDOG_24	(0x00000000)
-#define NETARM_GEN_SYS_CFG_WDOG_26	(0x00100000)
-#define NETARM_GEN_SYS_CFG_WDOG_28	(0x00200000)
-#define NETARM_GEN_SYS_CFG_WDOG_29	(0x00300000)
-
-#define NETARM_GEN_SYS_CFG_BUSMON_EN	(0x00040000)
-#define NETARM_GEN_SYS_CFG_BUSMON_128	(0x00000000)
-#define NETARM_GEN_SYS_CFG_BUSMON_64	(0x00010000)
-#define NETARM_GEN_SYS_CFG_BUSMON_32	(0x00020000)
-#define NETARM_GEN_SYS_CFG_BUSMON_16	(0x00030000)
-
-#define NETARM_GEN_SYS_CFG_USER_EN	(0x00008000)
-#define NETARM_GEN_SYS_CFG_BUSER_EN	(0x00004000)
-
-#define NETARM_GEN_SYS_CFG_BUSARB_INT	(0x00002000)
-#define NETARM_GEN_SYS_CFG_BUSARB_EXT	(0x00000000)
-
-#define NETARM_GEN_SYS_CFG_DMATST	(0x00001000)
-
-#define NETARM_GEN_SYS_CFG_TEALAST	(0x00000800)
-
-#define NETARM_GEN_SYS_CFG_ALIGN_ABORT	(0x00000400)
-
-#define NETARM_GEN_SYS_CFG_CACHE_EN	(0x00000200)
-
-#define NETARM_GEN_SYS_CFG_WRI_BUF_EN	(0x00000100)
-
-#define NETARM_GEN_SYS_CFG_CACHE_INIT	(0x00000080)
-
-/* PLL Control Register ( 0xFFB0_0008 ) */
-
-#define NETARM_GEN_PLL_CTL_PLLCNT_MASK	(0x0F000000)
-
-#define NETARM_GEN_PLL_CTL_PLLCNT(x)	(((x)<<24) & \
-					 NETARM_GEN_PLL_CTL_PLLCNT_MASK)
-
-/* Defaults for POLTST and ICP Fields in PLL CTL */
-#define NETARM_GEN_PLL_CTL_OUTDIV(x)	(x)
-#define NETARM_GEN_PLL_CTL_INDIV(x)	((x)<<6)
-#define NETARM_GEN_PLL_CTL_POLTST_DEF	(0x00000E00)
-#define NETARM_GEN_PLL_CTL_ICP_DEF	(0x0000003C)
-
-
-/* Software Service Register ( 0xFFB0_000C ) */
-
-#define NETARM_GEN_SW_SVC_RESETA	(0x123)
-#define NETARM_GEN_SW_SVC_RESETB	(0x321)
-
-/* PORT C Register ( 0xFFB0_0028 ) */
-
-#ifndef CONFIG_NETARM_NS7520
-#define NETARM_GEN_PORT_MODE(x)		(((x)<<24) + (0xFF00))
-#define NETARM_GEN_PORT_DIR(x)		(((x)<<16) + (0xFF00))
-#else
-#define NETARM_GEN_PORT_MODE(x)		((x)<<24)
-#define NETARM_GEN_PORT_DIR(x)		((x)<<16)
-#define NETARM_GEN_PORT_CSF(x)		((x)<<8)
-#endif
-
-/* Timer Registers ( 0xFFB0_0010 0xFFB0_0018 ) */
-
-#define NETARM_GEN_TCTL_ENABLE		(0x80000000)
-#define NETARM_GEN_TCTL_INT_ENABLE	(0x40000000)
-
-#define NETARM_GEN_TCTL_USE_IRQ		(0x00000000)
-#define NETARM_GEN_TCTL_USE_FIQ		(0x20000000)
-
-#define NETARM_GEN_TCTL_USE_PRESCALE	(0x10000000)
-#define NETARM_GEN_TCTL_INIT_COUNT(x)	((x) & 0x1FF)
-
-#define NETARM_GEN_TSTAT_INTPEN		(0x40000000)
-#if ~defined(CONFIG_NETARM_NS7520)
-#define NETARM_GEN_TSTAT_CTC_MASK	(0x000001FF)
-#else
-#define NETARM_GEN_TSTAT_CTC_MASK	(0x0FFFFFFF)
-#endif
-
-/* prescale to msecs conversion */
-
-#if !defined(CONFIG_NETARM_PLL_BYPASS)
-#define NETARM_GEN_TIMER_MSEC_P(x)	( ( ( 20480 ) * ( 0x1FF - ( (x) &	    \
-					    NETARM_GEN_TSTAT_CTC_MASK ) +   \
-					    1 ) ) / (NETARM_XTAL_FREQ/1000) )
-
-#define NETARM_GEN_TIMER_SET_HZ(x)	( ( ((NETARM_XTAL_FREQ/(20480*(x)))-1) & \
-					  NETARM_GEN_TSTAT_CTC_MASK ) | \
-					  NETARM_GEN_TCTL_USE_PRESCALE )
-
-#else
-#define NETARM_GEN_TIMER_MSEC_P(x)	( ( ( 4096 ) * ( 0x1FF - ( (x) &    \
-					    NETARM_GEN_TSTAT_CTC_MASK ) +   \
-					    1 ) ) / (NETARM_XTAL_FREQ/1000) )
-
-#define NETARM_GEN_TIMER_SET_HZ(x)	( ( ((NETARM_XTAL_FREQ/(4096*(x)))-1) & \
-					  NETARM_GEN_TSTAT_CTC_MASK ) | \
-					  NETARM_GEN_TCTL_USE_PRESCALE )
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h b/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h
deleted file mode 100644
index c650c3b..0000000
--- a/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * include/asm-armnommu/arch-netarm/netarm_mem_module.h
- *
- * Copyright (C) 2005
- * Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
- *
- * Copyright (C) 2000, 2001 NETsilicon, Inc.
- * Copyright (C) 2000, 2001 Red Hat, Inc.
- *
- * This software is copyrighted by Red Hat. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall Red Hat
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : Joe deBlaquiere
- *
- * Modified to support NS7520 by Art Shipkowski.
- */
-
-#ifndef __NETARM_MEM_MODULE_REGISTERS_H
-#define __NETARM_MEM_MODULE_REGISTERS_H
-
-/* GEN unit register offsets */
-
-#define	NETARM_MEM_MODULE_BASE		(0xFFC00000)
-
-#define	NETARM_MEM_MODULE_CONFIG	(0x00)
-#define	NETARM_MEM_CS0_BASE_ADDR	(0x10)
-#define	NETARM_MEM_CS0_OPTIONS		(0x14)
-#define	NETARM_MEM_CS1_BASE_ADDR	(0x20)
-#define	NETARM_MEM_CS1_OPTIONS		(0x24)
-#define	NETARM_MEM_CS2_BASE_ADDR	(0x30)
-#define	NETARM_MEM_CS2_OPTIONS		(0x34)
-#define	NETARM_MEM_CS3_BASE_ADDR	(0x40)
-#define	NETARM_MEM_CS3_OPTIONS		(0x44)
-#define	NETARM_MEM_CS4_BASE_ADDR	(0x50)
-#define	NETARM_MEM_CS4_OPTIONS		(0x54)
-
-/* select bitfield defintions */
-
-/* Module Configuration Register ( 0xFFC0_0000 ) */
-
-#define NETARM_MEM_CFG_REFR_COUNT_MASK	(0xFF000000)
-#define NETARM_MEM_CFG_REFRESH_EN	(0x00800000)
-
-#define NETARM_MEM_CFG_REFR_CYCLE_8CLKS	(0x00000000)
-#define NETARM_MEM_CFG_REFR_CYCLE_6CLKS	(0x00200000)
-#define NETARM_MEM_CFG_REFR_CYCLE_5CLKS	(0x00400000)
-#define NETARM_MEM_CFG_REFR_CYCLE_4CLKS	(0x00600000)
-
-#define NETARM_MEM_CFG_PORTC_AMUX	(0x00100000)
-
-#define NETARM_MEM_CFG_A27_ADDR		(0x00080000)
-#define NETARM_MEM_CFG_A27_CS0OE	(0x00000000)
-
-#define NETARM_MEM_CFG_A26_ADDR		(0x00040000)
-#define NETARM_MEM_CFG_A26_CS0WE	(0x00000000)
-
-#define NETARM_MEM_CFG_A25_ADDR		(0x00020000)
-#define NETARM_MEM_CFG_A25_BLAST	(0x00000000)
-
-#define NETARM_MEM_CFG_PORTC_AMUX2	(0x00010000)
-
-
-/* range on this period is about 1 to 275 usec (with 18.432MHz clock)   */
-/* the expression will round down, so make sure to reverse it to verify */
-/* it is what you want. period = [( count + 1 ) * 20] / Fcrystal        */
-/* (note: Fxtal = Fcrystal/5, see HWRefGuide sections 8.2.5 and 11.3.2) */
-
-#define	NETARM_MEM_REFR_PERIOD_USEC(p)	(NETARM_MEM_CFG_REFR_COUNT_MASK & \
-					 (((((NETARM_XTAL_FREQ/(1000))*p)/(20000) \
-					    ) - (1) ) << (24)))
-
-#if 0
-/* range on this period is about 1 to 275 usec (with 18.432MHz clock) */
-/* the expression will round down, so make sure to reverse it toverify */
-/* it is what you want. period = [( count + 1 ) * 4] / Fxtal          */
-
-#define	NETARM_MEM_REFR_PERIOD_USEC(p)	(NETARM_MEM_CFG_REFR_COUNT_MASK & \
-					 (((((NETARM_XTAL_FREQ/(1000))*p)/(4000) \
-					    ) - (1) ) << (24)))
-#endif
-
-/* Base Address Registers (0xFFC0_00X0) */
-
-#define NETARM_MEM_BAR_BASE_MASK	(0xFFFFF000)
-
-/* macro to define base */
-
-#define NETARM_MEM_BAR_BASE(x)		((x) & NETARM_MEM_BAR_BASE_MASK)
-
-#define NETARM_MEM_BAR_DRAM_FP		(0x00000000)
-#define NETARM_MEM_BAR_DRAM_EDO		(0x00000100)
-#define NETARM_MEM_BAR_DRAM_SYNC	(0x00000200)
-
-#define NETARM_MEM_BAR_DRAM_MUX_INT	(0x00000000)
-#define NETARM_MEM_BAR_DRAM_MUX_EXT	(0x00000080)
-
-#define NETARM_MEM_BAR_DRAM_MUX_BAL	(0x00000000)
-#define NETARM_MEM_BAR_DRAM_MUX_UNBAL	(0x00000020)
-
-#define NETARM_MEM_BAR_1BCLK_IDLE	(0x00000010)
-
-#define NETARM_MEM_BAR_DRAM_SEL		(0x00000008)
-
-#define NETARM_MEM_BAR_BURST_EN		(0x00000004)
-
-#define NETARM_MEM_BAR_WRT_PROT		(0x00000002)
-
-#define NETARM_MEM_BAR_VALID		(0x00000001)
-
-/* Option Registers (0xFFC0_00X4) */
-
-/* macro to define which bits of the base are significant */
-
-#define NETARM_MEM_OPT_BASE_USE(x)	((x) & NETARM_MEM_BAR_BASE_MASK)
-
-#define NETARM_MEM_OPT_WAIT_MASK	(0x00000F00)
-
-#define	NETARM_MEM_OPT_WAIT_STATES(x)	(((x) << 8 ) & NETARM_MEM_OPT_WAIT_MASK )
-
-#define NETARM_MEM_OPT_BCYC_1		(0x00000000)
-#define NETARM_MEM_OPT_BCYC_2		(0x00000040)
-#define NETARM_MEM_OPT_BCYC_3		(0x00000080)
-#define NETARM_MEM_OPT_BCYC_4		(0x000000C0)
-
-#define NETARM_MEM_OPT_BSIZE_2		(0x00000000)
-#define NETARM_MEM_OPT_BSIZE_4		(0x00000010)
-#define NETARM_MEM_OPT_BSIZE_8		(0x00000020)
-#define NETARM_MEM_OPT_BSIZE_16		(0x00000030)
-
-#define NETARM_MEM_OPT_32BIT		(0x00000000)
-#define NETARM_MEM_OPT_16BIT		(0x00000004)
-#define NETARM_MEM_OPT_8BIT		(0x00000008)
-#define NETARM_MEM_OPT_32BIT_EXT_ACK	(0x0000000C)
-
-#define NETARM_MEM_OPT_BUS_SIZE_MASK	(0x0000000C)
-
-#define NETARM_MEM_OPT_READ_ASYNC	(0x00000000)
-#define NETARM_MEM_OPT_READ_SYNC	(0x00000002)
-
-#define NETARM_MEM_OPT_WRITE_ASYNC	(0x00000000)
-#define NETARM_MEM_OPT_WRITE_SYNC	(0x00000001)
-
-#ifdef CONFIG_NETARM_NS7520
-/* The NS7520 has a second options register for each chip select */
-#define	NETARM_MEM_CS0_OPTIONS_B  (0x18)
-#define	NETARM_MEM_CS1_OPTIONS_B  (0x28)
-#define	NETARM_MEM_CS2_OPTIONS_B  (0x38)
-#define	NETARM_MEM_CS3_OPTIONS_B  (0x48)
-#define	NETARM_MEM_CS4_OPTIONS_B  (0x58)
-
-/* Option B Registers (0xFFC0_00x8) */
-#define NETARM_MEM_OPTB_SYNC_1_STAGE	(0x00000001)
-#define NETARM_MEM_OPTB_SYNC_2_STAGE	(0x00000002)
-#define NETARM_MEM_OPTB_BCYC_PLUS0	(0x00000000)
-#define NETARM_MEM_OPTB_BCYC_PLUS4	(0x00000004)
-#define NETARM_MEM_OPTB_BCYC_PLUS8	(0x00000008)
-#define NETARM_MEM_OPTB_BCYC_PLUS12	(0x0000000C)
-
-#define NETARM_MEM_OPTB_WAIT_PLUS0	(0x00000000)
-#define NETARM_MEM_OPTB_WAIT_PLUS16	(0x00000010)
-#define NETARM_MEM_OPTB_WAIT_PLUS32	(0x00000020)
-#define NETARM_MEM_OPTB_WAIT_PLUS48	(0x00000030)
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_registers.h b/arch/arm/include/asm/arch-arm720t/netarm_registers.h
deleted file mode 100644
index fa88128..0000000
--- a/arch/arm/include/asm/arch-arm720t/netarm_registers.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * linux/include/asm-arm/arch-netarm/netarm_registers.h
- *
- * Copyright (C) 2005
- * Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
- *
- * Copyright (C) 2000, 2001 NETsilicon, Inc.
- * Copyright (C) 2000, 2001 WireSpeed Communications Corporation
- *
- * This software is copyrighted by WireSpeed. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall WireSpeed
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : Joe deBlaquiere
- *
- * Modified to support NS7520 by Art Shipkowski.
- */
-
-#ifndef __NET_ARM_REGISTERS_H
-#define __NET_ARM_REGISTERS_H
-
-#include <config.h>
-
-/* fundamental constants : */
-/* the input crystal/clock frequency ( in Hz ) */
-#define	NETARM_XTAL_FREQ_25MHz		(18432000)
-#define	NETARM_XTAL_FREQ_33MHz		(23698000)
-#define	NETARM_XTAL_FREQ_48MHz		(48000000)
-#define	NETARM_XTAL_FREQ_55MHz		(55000000)
-#define NETARM_XTAL_FREQ_EMLIN1		(20000000)
-
-/* the frequency of SYS_CLK */
-#if defined(CONFIG_NETARM_EMLIN)
-
-/* EMLIN board:  33 MHz (exp.) */
-#define	NETARM_PLL_COUNT_VAL		6
-#define NETARM_XTAL_FREQ		NETARM_XTAL_FREQ_25MHz
-
-#elif defined(CONFIG_NETARM_NET40_REV2)
-
-/* NET+40 Rev2 boards:  33 MHz (with NETARM_XTAL_FREQ_25MHz) */
-#define	NETARM_PLL_COUNT_VAL		6
-#define	NETARM_XTAL_FREQ		NETARM_XTAL_FREQ_25MHz
-
-#elif defined(CONFIG_NETARM_NET40_REV4)
-
-/* NET+40 Rev4 boards with EDO must clock slower: 25 MHz (with
-   NETARM_XTAL_FREQ_25MHz) 4 */
-#define	NETARM_PLL_COUNT_VAL		4
-#define	NETARM_XTAL_FREQ		NETARM_XTAL_FREQ_25MHz
-
-#elif defined(CONFIG_NETARM_NET50)
-
-/* NET+50 boards:  40 MHz (with NETARM_XTAL_FREQ_25MHz) */
-#define NETARM_PLL_COUNT_VAL		8
-#define	NETARM_XTAL_FREQ		NETARM_XTAL_FREQ_25MHz
-
-#else	/* CONFIG_NETARM_NS7520 */
-
-#define	NETARM_PLL_COUNT_VAL		0
-
-#if defined(CONFIG_BOARD_UNC20)
-#define	NETARM_XTAL_FREQ		NETARM_XTAL_FREQ_48MHz
-#else
-#define	NETARM_XTAL_FREQ		NETARM_XTAL_FREQ_55MHz
-#endif
-
-#endif
-
-/* #include "arm_registers.h" */
-#include <asm/arch/netarm_gen_module.h>
-#include <asm/arch/netarm_mem_module.h>
-#include <asm/arch/netarm_ser_module.h>
-#include <asm/arch/netarm_eni_module.h>
-#include <asm/arch/netarm_dma_module.h>
-#include <asm/arch/netarm_eth_module.h>
-
-#endif
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_ser_module.h b/arch/arm/include/asm/arch-arm720t/netarm_ser_module.h
deleted file mode 100644
index 6fbae11..0000000
--- a/arch/arm/include/asm/arch-arm720t/netarm_ser_module.h
+++ /dev/null
@@ -1,347 +0,0 @@
-/*
- * linux/include/asm-arm/arch-netarm/netarm_ser_module.h
- *
- * Copyright (C) 2000 NETsilicon, Inc.
- * Copyright (C) 2000 Red Hat, Inc.
- *
- * This software is copyrighted by Red Hat. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall Red Hat
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : Joe deBlaquiere
- *             Clark Williams
- */
-
-#ifndef __NETARM_SER_MODULE_REGISTERS_H
-#define __NETARM_SER_MODULE_REGISTERS_H
-
-#ifndef	__ASSEMBLER__
-
-/* (--sub)#include "types.h" */
-
-/* serial channel control structure */
-typedef struct {
-  u32	ctrl_a;
-  u32	ctrl_b;
-  u32	status_a;
-  u32	bitrate;
-  u32	fifo;
-  u32	rx_buf_timer;
-  u32	rx_char_timer;
-  u32	rx_match;
-  u32	rx_match_mask;
-  u32	ctrl_c;
-  u32	status_b;
-  u32	status_c;
-  u32	fifo_last;
-  u32	unused[3];
-} netarm_serial_channel_t;
-
-#endif
-
-/* SER unit register offsets */
-
-/* #ifdef CONFIG_ARCH_NETARM */
-#define	NETARM_SER_MODULE_BASE		(0xFFD00000)
-/* #else */
-/* extern serial_channel_t netarm_dummy_registers[]; */
-/* #define NETARM_SER_MODULE_BASE		(netarm_dummy_registers) */
-/* #ifndef NETARM_XTAL_FREQ */
-/* #define NETARM_XTAL_FREQ                18432000 */
-/* #endif */
-/* #endif */
-
-/* calculate the sysclk value from the pll setting */
-#define	NETARM_PLLED_SYSCLK_FREQ	(( NETARM_XTAL_FREQ / 5 ) * \
-					 ( NETARM_PLL_COUNT_VAL + 3 ))
-
-#define get_serial_channel(c) (&(((netarm_serial_channel_t *)NETARM_SER_MODULE_BASE)[c]))
-
-#define	NETARM_SER_CH1_CTRL_A		(0x00)
-#define	NETARM_SER_CH1_CTRL_B		(0x04)
-#define	NETARM_SER_CH1_STATUS_A		(0x08)
-#define	NETARM_SER_CH1_BITRATE		(0x0C)
-#define	NETARM_SER_CH1_FIFO		(0x10)
-#define	NETARM_SER_CH1_RX_BUF_TMR	(0x14)
-#define	NETARM_SER_CH1_RX_CHAR_TMR	(0x18)
-#define	NETARM_SER_CH1_RX_MATCH		(0x1c)
-#define	NETARM_SER_CH1_RX_MATCH_MASK	(0x20)
-#define	NETARM_SER_CH1_CTRL_C		(0x24)
-#define	NETARM_SER_CH1_STATUS_B		(0x28)
-#define	NETARM_SER_CH1_STATUS_C		(0x2c)
-#define	NETARM_SER_CH1_FIFO_LAST	(0x30)
-
-#define	NETARM_SER_CH2_CTRL_A		(0x40)
-#define	NETARM_SER_CH2_CTRL_B		(0x44)
-#define	NETARM_SER_CH2_STATUS_A		(0x48)
-#define	NETARM_SER_CH2_BITRATE		(0x4C)
-#define	NETARM_SER_CH2_FIFO		(0x50)
-#define	NETARM_SER_CH2_RX_BUF_TMR	(0x54)
-#define	NETARM_SER_CH2_RX_CHAR_TMR	(0x58)
-#define	NETARM_SER_CH2_RX_MATCH		(0x5c)
-#define	NETARM_SER_CH2_RX_MATCH_MASK	(0x60)
-#define	NETARM_SER_CH2_CTRL_C		(0x64)
-#define	NETARM_SER_CH2_STATUS_B		(0x68)
-#define	NETARM_SER_CH2_STATUS_C		(0x6c)
-#define	NETARM_SER_CH2_FIFO_LAST	(0x70)
-
-/* select bitfield defintions */
-
-/* Control Register A */
-
-#define	NETARM_SER_CTLA_ENABLE		(0x80000000)
-#define	NETARM_SER_CTLA_BRK		(0x40000000)
-
-#define	NETARM_SER_CTLA_STICKP		(0x20000000)
-
-#define	NETARM_SER_CTLA_P_EVEN		(0x18000000)
-#define	NETARM_SER_CTLA_P_ODD		(0x08000000)
-#define	NETARM_SER_CTLA_P_NONE		(0x00000000)
-
-/* if you read the errata, you will find that the STOP bits don't work right */
-#define	NETARM_SER_CTLA_2STOP		(0x00000000)
-#define	NETARM_SER_CTLA_3STOP		(0x04000000)
-
-#define	NETARM_SER_CTLA_5BITS		(0x00000000)
-#define	NETARM_SER_CTLA_6BITS		(0x01000000)
-#define	NETARM_SER_CTLA_7BITS		(0x02000000)
-#define	NETARM_SER_CTLA_8BITS		(0x03000000)
-
-#define	NETARM_SER_CTLA_CTSTX		(0x00800000)
-#define	NETARM_SER_CTLA_RTSRX		(0x00400000)
-
-#define	NETARM_SER_CTLA_LOOP_REM	(0x00200000)
-#define	NETARM_SER_CTLA_LOOP_LOC	(0x00100000)
-
-#define	NETARM_SER_CTLA_GPIO2		(0x00080000)
-#define	NETARM_SER_CTLA_GPIO1		(0x00040000)
-
-#define	NETARM_SER_CTLA_DTR_EN		(0x00020000)
-#define	NETARM_SER_CTLA_RTS_EN		(0x00010000)
-
-#define	NETARM_SER_CTLA_IE_RX_BRK	(0x00008000)
-#define	NETARM_SER_CTLA_IE_RX_FRMERR	(0x00004000)
-#define	NETARM_SER_CTLA_IE_RX_PARERR	(0x00002000)
-#define	NETARM_SER_CTLA_IE_RX_OVERRUN	(0x00001000)
-#define	NETARM_SER_CTLA_IE_RX_RDY	(0x00000800)
-#define	NETARM_SER_CTLA_IE_RX_HALF	(0x00000400)
-#define	NETARM_SER_CTLA_IE_RX_FULL	(0x00000200)
-#define	NETARM_SER_CTLA_IE_RX_DMAEN	(0x00000100)
-#define	NETARM_SER_CTLA_IE_RX_DCD	(0x00000080)
-#define	NETARM_SER_CTLA_IE_RX_RI	(0x00000040)
-#define	NETARM_SER_CTLA_IE_RX_DSR	(0x00000020)
-
-#define NETARM_SER_CTLA_IE_RX_ALL	(NETARM_SER_CTLA_IE_RX_BRK \
-					|NETARM_SER_CTLA_IE_RX_FRMERR \
-					|NETARM_SER_CTLA_IE_RX_PARERR \
-					|NETARM_SER_CTLA_IE_RX_OVERRUN \
-					|NETARM_SER_CTLA_IE_RX_RDY \
-					|NETARM_SER_CTLA_IE_RX_HALF \
-					|NETARM_SER_CTLA_IE_RX_FULL \
-					|NETARM_SER_CTLA_IE_RX_DMAEN \
-					|NETARM_SER_CTLA_IE_RX_DCD \
-					|NETARM_SER_CTLA_IE_RX_RI \
-					|NETARM_SER_CTLA_IE_RX_DSR)
-
-#define	NETARM_SER_CTLA_IE_TX_CTS	(0x00000010)
-#define	NETARM_SER_CTLA_IE_TX_EMPTY	(0x00000008)
-#define	NETARM_SER_CTLA_IE_TX_HALF	(0x00000004)
-#define	NETARM_SER_CTLA_IE_TX_FULL	(0x00000002)
-#define	NETARM_SER_CTLA_IE_TX_DMAEN	(0x00000001)
-
-#define NETARM_SER_CTLA_IE_TX_ALL	(NETARM_SER_CTLA_IE_TX_CTS \
-					|NETARM_SER_CTLA_IE_TX_EMPTY \
-					|NETARM_SER_CTLA_IE_TX_HALF \
-					|NETARM_SER_CTLA_IE_TX_FULL \
-					|NETARM_SER_CTLA_IE_TX_DMAEN)
-
-/* Control Register B */
-
-#define	NETARM_SER_CTLB_MATCH1_EN	(0x80000000)
-#define	NETARM_SER_CTLB_MATCH2_EN	(0x40000000)
-#define	NETARM_SER_CTLB_MATCH3_EN	(0x20000000)
-#define	NETARM_SER_CTLB_MATCH4_EN	(0x10000000)
-
-#define	NETARM_SER_CTLB_RBGT_EN		(0x08000000)
-#define	NETARM_SER_CTLB_RCGT_EN		(0x04000000)
-
-#define	NETARM_SER_CTLB_UART_MODE	(0x00000000)
-#define	NETARM_SER_CTLB_HDLC_MODE	(0x00100000)
-#define	NETARM_SER_CTLB_SPI_MAS_MODE	(0x00200000)
-#define	NETARM_SER_CTLB_SPI_SLV_MODE	(0x00300000)
-
-#define	NETARM_SER_CTLB_REV_BIT_ORDER	(0x00080000)
-
-#define	NETARM_SER_CTLB_MAM1		(0x00040000)
-#define	NETARM_SER_CTLB_MAM2		(0x00020000)
-
-/* Status Register A */
-
-#define	NETARM_SER_STATA_MATCH1		(0x80000000)
-#define	NETARM_SER_STATA_MATCH2		(0x40000000)
-#define	NETARM_SER_STATA_MATCH3		(0x20000000)
-#define	NETARM_SER_STATA_MATCH4		(0x10000000)
-
-#define	NETARM_SER_STATA_BGAP		(0x80000000)
-#define	NETARM_SER_STATA_CGAP		(0x40000000)
-
-#define	NETARM_SER_STATA_RX_1B		(0x00100000)
-#define	NETARM_SER_STATA_RX_2B		(0x00200000)
-#define	NETARM_SER_STATA_RX_3B		(0x00300000)
-#define	NETARM_SER_STATA_RX_4B		(0x00000000)
-
-/* downshifted values */
-
-#define	NETARM_SER_STATA_RXFDB_1BYTES	(0x001)
-#define	NETARM_SER_STATA_RXFDB_2BYTES	(0x002)
-#define	NETARM_SER_STATA_RXFDB_3BYTES	(0x003)
-#define	NETARM_SER_STATA_RXFDB_4BYTES	(0x000)
-
-#define	NETARM_SER_STATA_RXFDB_MASK	(0x00300000)
-#define	NETARM_SER_STATA_RXFDB(x)	(((x) & NETARM_SER_STATA_RXFDB_MASK) \
-					 >> 20)
-
-#define	NETARM_SER_STATA_DCD		(0x00080000)
-#define	NETARM_SER_STATA_RI		(0x00040000)
-#define	NETARM_SER_STATA_DSR		(0x00020000)
-#define	NETARM_SER_STATA_CTS		(0x00010000)
-
-#define	NETARM_SER_STATA_RX_BRK		(0x00008000)
-#define	NETARM_SER_STATA_RX_FRMERR	(0x00004000)
-#define	NETARM_SER_STATA_RX_PARERR	(0x00002000)
-#define	NETARM_SER_STATA_RX_OVERRUN	(0x00001000)
-#define	NETARM_SER_STATA_RX_RDY		(0x00000800)
-#define	NETARM_SER_STATA_RX_HALF	(0x00000400)
-#define	NETARM_SER_STATA_RX_CLOSED	(0x00000200)
-#define	NETARM_SER_STATA_RX_FULL	(0x00000100)
-#define	NETARM_SER_STATA_RX_DCD		(0x00000080)
-#define	NETARM_SER_STATA_RX_RI		(0x00000040)
-#define	NETARM_SER_STATA_RX_DSR		(0x00000020)
-
-#define	NETARM_SER_STATA_TX_CTS		(0x00000010)
-#define	NETARM_SER_STATA_TX_RDY		(0x00000008)
-#define	NETARM_SER_STATA_TX_HALF	(0x00000004)
-#define	NETARM_SER_STATA_TX_FULL	(0x00000002)
-#define	NETARM_SER_STATA_TX_DMAEN	(0x00000001)
-
-/* you have to clear all receive signals to get the fifo to move forward */
-#define NETARM_SER_STATA_CLR_ALL	(NETARM_SER_STATA_RX_BRK | \
-					 NETARM_SER_STATA_RX_FRMERR | \
-					 NETARM_SER_STATA_RX_PARERR | \
-					 NETARM_SER_STATA_RX_OVERRUN | \
-					 NETARM_SER_STATA_RX_HALF | \
-					 NETARM_SER_STATA_RX_CLOSED | \
-					 NETARM_SER_STATA_RX_FULL | \
-					 NETARM_SER_STATA_RX_DCD | \
-					 NETARM_SER_STATA_RX_RI | \
-					 NETARM_SER_STATA_RX_DSR | \
-					 NETARM_SER_STATA_TX_CTS )
-
-/* Bit Rate Registers */
-
-#define	NETARM_SER_BR_EN		(0x80000000)
-#define	NETARM_SER_BR_TMODE		(0x40000000)
-
-#define	NETARM_SER_BR_RX_CLK_INT	(0x00000000)
-#define	NETARM_SER_BR_RX_CLK_EXT	(0x20000000)
-#define	NETARM_SER_BR_TX_CLK_INT	(0x00000000)
-#define	NETARM_SER_BR_TX_CLK_EXT	(0x10000000)
-
-#define	NETARM_SER_BR_RX_CLK_DRV	(0x08000000)
-#define	NETARM_SER_BR_TX_CLK_DRV	(0x04000000)
-
-#define	NETARM_SER_BR_CLK_EXT_5		(0x00000000)
-#define	NETARM_SER_BR_CLK_SYSTEM	(0x01000000)
-#define	NETARM_SER_BR_CLK_OUT1A		(0x02000000)
-#define	NETARM_SER_BR_CLK_OUT2A		(0x03000000)
-
-#define	NETARM_SER_BR_TX_CLK_INV	(0x00800000)
-#define	NETARM_SER_BR_RX_CLK_INV	(0x00400000)
-
-/* complete settings assuming system clock input is 18MHz */
-
-#define	NETARM_SER_BR_MASK		(0x000007FF)
-
-/* bit rate determined from equation Fbr = Fxtal / [ 10 * ( N + 1 ) ] */
-/* from section 7.5.4 of HW Ref Guide */
-
-/* #ifdef CONFIG_NETARM_PLL_BYPASS */
-#define	NETARM_SER_BR_X16(x)	( NETARM_SER_BR_EN |			\
-				  NETARM_SER_BR_RX_CLK_INT |		\
-				  NETARM_SER_BR_TX_CLK_INT |		\
-				  NETARM_SER_BR_CLK_EXT_5 |		\
-				  ( ( ( ( NETARM_XTAL_FREQ /		\
-				          ( x * 10 ) ) - 1 ) /	16 ) &	\
-				    NETARM_SER_BR_MASK ) )
-/*
-#else
-#define	NETARM_SER_BR_X16(x)	( NETARM_SER_BR_EN |			\
-				  NETARM_SER_BR_RX_CLK_INT |		\
-				  NETARM_SER_BR_TX_CLK_INT |		\
-				  NETARM_SER_BR_CLK_SYSTEM |		\
-				  ( ( ( ( NETARM_PLLED_SYSCLK_FREQ /		\
-				          ( x * 2 ) ) - 1 ) /	16 ) &	\
-				    NETARM_SER_BR_MASK ) )
-#endif
-*/
-
-/* Receive Buffer Gap Timer */
-
-#define	NETARM_SER_RX_GAP_TIMER_EN	(0x80000000)
-#define	NETARM_SER_RX_GAP_MASK		(0x00003FFF)
-
-/* rx gap is a function of bit rate x */
-
-/* #ifdef CONFIG_NETARM_PLL_BYPASS */
-#define	NETARM_SER_RXGAP(x)	( NETARM_SER_RX_GAP_TIMER_EN |		\
-				  ( ( ( ( 10 * NETARM_XTAL_FREQ ) /	\
-				        ( x * 5 * 512 ) ) - 1 ) &	\
-			              NETARM_SER_RX_GAP_MASK ) )
-/*
-#else
-#define	NETARM_SER_RXGAP(x)	( NETARM_SER_RX_GAP_TIMER_EN |			\
-				  ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) /	\
-				        ( x * 512 ) ) - 1 ) &			\
-			              NETARM_SER_RX_GAP_MASK ) )
-#endif
-*/
-
-#if 0
-#define	NETARM_SER_RXGAP(x)	( NETARM_SER_RX_GAP_TIMER_EN |		\
-				  ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) /	\
-				        ( x * 5 * 512 ) ) - 1 ) &	\
-			              NETARM_SER_RX_GAP_MASK ) )
-#define	NETARM_SER_RXGAP(x)	( NETARM_SER_RX_GAP_TIMER_EN |		\
-				  ( ( ( ( 10 * NETARM_XTAL_FREQ ) /	\
-				        ( x * 512 ) ) - 1 ) &	\
-			              NETARM_SER_RX_GAP_MASK ) )
-#endif
-
-#define MIN_BAUD_RATE        600
-#define MAX_BAUD_RATE     115200
-
-/* the default BAUD rate for the BOOTLOADER, there is a separate */
-/* setting in the serial driver <arch/armnommu/drivers/char/serial-netarm.h> */
-#define DEFAULT_BAUD_RATE 9600
-#define NETARM_SER_FIFO_SIZE 32
-#define MIN_GAP 0
-
-#endif
diff --git a/arch/arm/include/asm/arch-lpc2292/lpc2292_registers.h b/arch/arm/include/asm/arch-lpc2292/lpc2292_registers.h
deleted file mode 100644
index 5715f3e..0000000
--- a/arch/arm/include/asm/arch-lpc2292/lpc2292_registers.h
+++ /dev/null
@@ -1,225 +0,0 @@
-#ifndef __LPC2292_REGISTERS_H
-#define __LPC2292_REGISTERS_H
-
-#include <config.h>
-
-/* Macros for reading/writing registers */
-#define PUT8(reg, value) (*(volatile unsigned char*)(reg) = (value))
-#define PUT16(reg, value) (*(volatile unsigned short*)(reg) = (value))
-#define PUT32(reg, value) (*(volatile unsigned int*)(reg) = (value))
-#define GET8(reg) (*(volatile unsigned char*)(reg))
-#define GET16(reg) (*(volatile unsigned short*)(reg))
-#define GET32(reg) (*(volatile unsigned int*)(reg))
-
-/* External Memory Controller */
-
-#define BCFG0 0xFFE00000	/* 32-bits */
-#define BCFG1 0xFFE00004	/* 32-bits */
-#define BCFG2 0xFFE00008	/* 32-bits */
-#define BCFG3 0xFFE0000c	/* 32-bits */
-
-/* System Control Block */
-
-#define EXTINT   0xE01FC140
-#define EXTWAKE  0xE01FC144
-#define EXTMODE  0xE01FC148
-#define EXTPOLAR 0xE01FC14C
-#define MEMMAP   0xE01FC040
-#define PLLCON   0xE01FC080
-#define PLLCFG   0xE01FC084
-#define PLLSTAT  0xE01FC088
-#define PLLFEED  0xE01FC08C
-#define PCON     0xE01FC0C0
-#define PCONP    0xE01FC0C4
-#define VPBDIV   0xE01FC100
-
-/* Memory Acceleration Module */
-
-#define MAMCR  0xE01FC000
-#define MAMTIM 0xE01FC004
-
-/* Vectored Interrupt Controller */
-
-#define VICIRQStatus    0xFFFFF000
-#define VICFIQStatus    0xFFFFF004
-#define VICRawIntr      0xFFFFF008
-#define VICIntSelect    0xFFFFF00C
-#define VICIntEnable    0xFFFFF010
-#define VICIntEnClr     0xFFFFF014
-#define VICSoftInt      0xFFFFF018
-#define VICSoftIntClear 0xFFFFF01C
-#define VICProtection   0xFFFFF020
-#define VICVectAddr     0xFFFFF030
-#define VICDefVectAddr  0xFFFFF034
-#define VICVectAddr0    0xFFFFF100
-#define VICVectAddr1    0xFFFFF104
-#define VICVectAddr2    0xFFFFF108
-#define VICVectAddr3    0xFFFFF10C
-#define VICVectAddr4    0xFFFFF110
-#define VICVectAddr5    0xFFFFF114
-#define VICVectAddr6    0xFFFFF118
-#define VICVectAddr7    0xFFFFF11C
-#define VICVectAddr8    0xFFFFF120
-#define VICVectAddr9    0xFFFFF124
-#define VICVectAddr10   0xFFFFF128
-#define VICVectAddr11   0xFFFFF12C
-#define VICVectAddr12   0xFFFFF130
-#define VICVectAddr13   0xFFFFF134
-#define VICVectAddr14   0xFFFFF138
-#define VICVectAddr15   0xFFFFF13C
-#define VICVectCntl0    0xFFFFF200
-#define VICVectCntl1	0xFFFFF204
-#define VICVectCntl2	0xFFFFF208
-#define VICVectCntl3	0xFFFFF20C
-#define VICVectCntl4	0xFFFFF210
-#define VICVectCntl5	0xFFFFF214
-#define VICVectCntl6	0xFFFFF218
-#define VICVectCntl7	0xFFFFF21C
-#define VICVectCntl8	0xFFFFF220
-#define VICVectCntl9	0xFFFFF224
-#define VICVectCntl10	0xFFFFF228
-#define VICVectCntl11	0xFFFFF22C
-#define VICVectCntl12	0xFFFFF230
-#define VICVectCntl13	0xFFFFF234
-#define VICVectCntl14	0xFFFFF238
-#define VICVectCntl15	0xFFFFF23C
-
-/* Pin connect block */
-
-#define PINSEL0 0xE002C000	/* 32 bits */
-#define PINSEL1 0xE002C004	/* 32 bits */
-#define PINSEL2 0xE002C014	/* 32 bits */
-
-/* GPIO */
-
-#define IO0PIN 0xE0028000
-#define IO0SET 0xE0028004
-#define IO0DIR 0xE0028008
-#define IO0CLR 0xE002800C
-#define IO1PIN 0xE0028010
-#define IO1SET 0xE0028014
-#define IO1DIR 0xE0028018
-#define IO1CLR 0xE002801C
-#define IO2PIN 0xE0028020
-#define IO2SET 0xE0028024
-#define IO2DIR 0xE0028028
-#define IO2CLR 0xE002802C
-#define IO3PIN 0xE0028030
-#define IO3SET 0xE0028034
-#define IO3DIR 0xE0028038
-#define IO3CLR 0xE002803C
-
-/* Uarts */
-
-#define U0RBR 0xE000C000
-#define U0THR 0xE000C000
-#define U0IER 0xE000C004
-#define U0IIR 0xE000C008
-#define U0FCR 0xE000C008
-#define U0LCR 0xE000C00C
-#define U0LSR 0xE000C014
-#define U0SCR 0xE000C01C
-#define U0DLL 0xE000C000
-#define U0DLM 0xE000C004
-
-#define U1RBR 0xE0010000
-#define U1THR 0xE0010000
-#define U1IER 0xE0010004
-#define U1IIR 0xE0010008
-#define U1FCR 0xE0010008
-#define U1LCR 0xE001000C
-#define U1MCR 0xE0010010
-#define U1LSR 0xE0010014
-#define U1MSR 0xE0010018
-#define U1SCR 0xE001001C
-#define U1DLL 0xE0010000
-#define U1DLM 0xE0010004
-
-/* I2C */
-
-#define I2CONSET 0xE001C000
-#define I2STAT   0xE001C004
-#define I2DAT    0xE001C008
-#define I2ADR    0xE001C00C
-#define I2SCLH   0xE001C010
-#define I2SCLL   0xE001C014
-#define I2CONCLR 0xE001C018
-
-/* SPI */
-
-#define S0SPCR  0xE0020000
-#define S0SPSR  0xE0020004
-#define S0SPDR  0xE0020008
-#define S0SPCCR 0xE002000C
-#define S0SPINT 0xE002001C
-
-#define S1SPCR  0xE0030000
-#define S1SPSR  0xE0030004
-#define S1SPDR  0xE0030008
-#define S1SPCCR 0xE003000C
-#define S1SPINT 0xE003001C
-
-/* CAN controller */
-
-/* skip for now */
-
-/* Timers */
-
-#define T0IR  0xE0004000
-#define T0TCR 0xE0004004
-#define T0TC  0xE0004008
-#define T0PR  0xE000400C
-#define T0PC  0xE0004010
-#define T0MCR 0xE0004014
-#define T0MR0 0xE0004018
-#define T0MR1 0xE000401C
-#define T0MR2 0xE0004020
-#define T0MR3 0xE0004024
-#define T0CCR 0xE0004028
-#define T0CR0 0xE000402C
-#define T0CR1 0xE0004030
-#define T0CR2 0xE0004034
-#define T0CR3 0xE0004038
-#define T0EMR 0xE000403C
-
-#define T1IR  0xE0008000
-#define T1TCR 0xE0008004
-#define T1TC  0xE0008008
-#define T1PR  0xE000800C
-#define T1PC  0xE0008010
-#define T1MCR 0xE0008014
-#define T1MR0 0xE0008018
-#define T1MR1 0xE000801C
-#define T1MR2 0xE0008020
-#define T1MR3 0xE0008024
-#define T1CCR 0xE0008028
-#define T1CR0 0xE000802C
-#define T1CR1 0xE0008030
-#define T1CR2 0xE0008034
-#define T1CR3 0xE0008038
-#define T1EMR 0xE000803C
-
-/* PWM */
-
-/* skip for now */
-
-/* A/D converter */
-
-/* skip for now */
-
-/* Real Time Clock */
-
-/* skip for now */
-
-/* Watchdog */
-
-#define WDMOD  0xE0000000
-#define WDTC   0xE0000004
-#define WDFEED 0xE0000008
-#define WDTV   0xE000000C
-
-/* EmbeddedICE LOGIC */
-
-/* skip for now */
-
-#endif
diff --git a/arch/arm/include/asm/arch-lpc2292/spi.h b/arch/arm/include/asm/arch-lpc2292/spi.h
deleted file mode 100644
index 6ae66e8..0000000
--- a/arch/arm/include/asm/arch-lpc2292/spi.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
-    This file defines the interface to the lpc22xx SPI module.
-    Copyright (C) 2006  Embedded Artists AB (www.embeddedartists.com)
-
-    This file may be included in software not adhering to the GPL.
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#ifndef SPI_H
-#define SPI_H
-
-#include <config.h>
-#include <common.h>
-#include <asm/errno.h>
-#include <asm/arch/hardware.h>
-
-#define SPIF 0x80
-
-#define spi_lock() disable_interrupts();
-#define spi_unlock() enable_interrupts();
-
-extern unsigned long spi_flags;
-extern unsigned char spi_idle;
-
-int spi_init(void);
-
-static inline unsigned char spi_read(void)
-{
-	unsigned char b;
-
-	PUT8(S0SPDR, spi_idle);
-	while (!(GET8(S0SPSR) & SPIF));
-	b = GET8(S0SPDR);
-
-	return b;
-}
-
-static inline void spi_write(unsigned char b)
-{
-	PUT8(S0SPDR, b);
-	while (!(GET8(S0SPSR) & SPIF));
-	GET8(S0SPDR);		/* this will clear the SPIF bit */
-}
-
-static inline void spi_set_clock(unsigned char clk_value)
-{
-	PUT8(S0SPCCR, clk_value);
-}
-
-static inline void spi_set_cfg(unsigned char phase,
-			       unsigned char polarity,
-			       unsigned char lsbf)
-{
-	unsigned char v = 0x20;	/* master bit set */
-
-	if (phase)
-		v |= 0x08;			/* set phase bit */
-	if (polarity) {
-		v |= 0x10;			/* set polarity bit */
-		spi_idle = 0xFF;
-	} else {
-		spi_idle = 0x00;
-	}
-	if (lsbf)
-		v |= 0x40;			/* set lsbf bit */
-
-	PUT8(S0SPCR, v);
-}
-#endif /* SPI_H */
diff --git a/arch/arm/include/asm/arch-omap3/dss.h b/arch/arm/include/asm/arch-omap3/dss.h
index 54add4b..ffaffbb 100644
--- a/arch/arm/include/asm/arch-omap3/dss.h
+++ b/arch/arm/include/asm/arch-omap3/dss.h
@@ -190,6 +190,7 @@ struct panel_config {
 
 #define PANEL_TIMING_H(bp, fp, sw) (DSS_HBP(bp) | DSS_HFP(fp) | DSS_HSW(sw))
 #define PANEL_TIMING_V(bp, fp, sw) (DSS_VBP(bp) | DSS_VFP(fp) | DSS_VSW(sw))
+#define PANEL_LCD_SIZE(xres, yres) ((yres - 1) << 16 | (xres - 1))
 
 /* Generic DSS Functions */
 void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
diff --git a/arch/arm/include/asm/arch-s3c4510b/hardware.h b/arch/arm/include/asm/arch-s3c4510b/hardware.h
deleted file mode 100644
index 6b8c8ed..0000000
--- a/arch/arm/include/asm/arch-s3c4510b/hardware.h
+++ /dev/null
@@ -1,272 +0,0 @@
-#ifndef __HW_S3C4510_H
-#define __HW_S3C4510_H
-
-/*
- * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
- * Curt Brune <curt@cucy.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Description:   Samsung S3C4510B register layout
- */
-
-/*------------------------------------------------------------------------
- *	  ASIC Address Definition
- *----------------------------------------------------------------------*/
-
-/* L1 8KB on chip SRAM base address */
-#define SRAM_BASE       (0x03fe0000)
-
-/* Special Register Start Address After System Reset */
-#define REG_BASE	(0x03ff0000)
-#define SPSTR		(REG_BASE)
-
-/* *********************** */
-/* System Manager Register */
-/* *********************** */
-#define REG_SYSCFG	(REG_BASE+0x0000)
-
-#define REG_CLKCON      (REG_BASE+0x3000)
-#define REG_EXTACON0	(REG_BASE+0x3008)
-#define REG_EXTACON1	(REG_BASE+0x300c)
-#define REG_EXTDBWTH	(REG_BASE+0x3010)
-#define REG_ROMCON0	(REG_BASE+0x3014)
-#define REG_ROMCON1	(REG_BASE+0x3018)
-#define REG_ROMCON2	(REG_BASE+0x301c)
-#define REG_ROMCON3	(REG_BASE+0x3020)
-#define REG_ROMCON4	(REG_BASE+0x3024)
-#define REG_ROMCON5	(REG_BASE+0x3028)
-#define REG_DRAMCON0	(REG_BASE+0x302c)
-#define REG_DRAMCON1	(REG_BASE+0x3030)
-#define REG_DRAMCON2	(REG_BASE+0x3034)
-#define REG_DRAMCON3	(REG_BASE+0x3038)
-#define REG_REFEXTCON	(REG_BASE+0x303c)
-
-/* *********************** */
-/* Ethernet BDMA Register  */
-/* *********************** */
-#define REG_BDMATXCON	(REG_BASE+0x9000)
-#define REG_BDMARXCON	(REG_BASE+0x9004)
-#define REG_BDMATXPTR	(REG_BASE+0x9008)
-#define REG_BDMARXPTR	(REG_BASE+0x900c)
-#define REG_BDMARXLSZ	(REG_BASE+0x9010)
-#define REG_BDMASTAT	(REG_BASE+0x9014)
-
-/* Content Address Memory */
-#define REG_CAM_BASE	(REG_BASE+0x9100)
-
-#define REG_BDMATXBUF	(REG_BASE+0x9200)
-#define REG_BDMARXBUF	(REG_BASE+0x9800)
-
-/* *********************** */
-/* Ethernet MAC Register   */
-/* *********************** */
-#define REG_MACCON	(REG_BASE+0xa000)
-#define REG_CAMCON	(REG_BASE+0xa004)
-#define REG_MACTXCON	(REG_BASE+0xa008)
-#define REG_MACTXSTAT	(REG_BASE+0xa00c)
-#define REG_MACRXCON	(REG_BASE+0xa010)
-#define REG_MACRXSTAT	(REG_BASE+0xa014)
-#define REG_STADATA	(REG_BASE+0xa018)
-#define REG_STACON	(REG_BASE+0xa01c)
-#define REG_CAMEN	(REG_BASE+0xa028)
-#define REG_EMISSCNT	(REG_BASE+0xa03c)
-#define REG_EPZCNT	(REG_BASE+0xa040)
-#define REG_ERMPZCNT	(REG_BASE+0xa044)
-#define REG_ETXSTAT	(REG_BASE+0x9040)
-#define REG_MACRXDESTR	(REG_BASE+0xa064)
-#define REG_MACRXSTATEM	(REG_BASE+0xa090)
-#define REG_MACRXFIFO	(REG_BASE+0xa200)
-
-/********************/
-/* I2C Bus Register */
-/********************/
-#define REG_I2C_CON	(REG_BASE+0xf000)
-#define REG_I2C_BUF	(REG_BASE+0xf004)
-#define REG_I2C_PS	(REG_BASE+0xf008)
-#define REG_I2C_COUNT	(REG_BASE+0xf00c)
-
-/********************/
-/*    GDMA 0        */
-/********************/
-#define REG_GDMACON0	(REG_BASE+0xb000)
-#define REG_GDMA0_RUN_ENABLE (REG_BASE+0xb020)
-#define REG_GDMASRC0	(REG_BASE+0xb004)
-#define REG_GDMADST0	(REG_BASE+0xb008)
-#define REG_GDMACNT0	(REG_BASE+0xb00c)
-
-/********************/
-/*    GDMA 1        */
-/********************/
-#define REG_GDMACON1	(REG_BASE+0xc000)
-#define REG_GDMA1_RUN_ENABLE (REG_BASE+0xc020)
-#define REG_GDMASRC1	(REG_BASE+0xc004)
-#define REG_GDMADST1	(REG_BASE+0xc008)
-#define REG_GDMACNT1	(REG_BASE+0xc00c)
-
-/********************/
-/*      UART 0      */
-/********************/
-#define UART0_BASE       (REG_BASE+0xd000)
-#define REG_UART0_LCON   (REG_BASE+0xd000)
-#define REG_UART0_CTRL   (REG_BASE+0xd004)
-#define REG_UART0_STAT   (REG_BASE+0xd008)
-#define REG_UART0_TXB    (REG_BASE+0xd00c)
-#define REG_UART0_RXB    (REG_BASE+0xd010)
-#define REG_UART0_BAUD_DIV    (REG_BASE+0xd014)
-#define REG_UART0_BAUD_CNT    (REG_BASE+0xd018)
-#define REG_UART0_BAUD_CLK    (REG_BASE+0xd01C)
-
-/********************/
-/*     UART 1       */
-/********************/
-#define UART1_BASE       (REG_BASE+0xe000)
-#define REG_UART1_LCON   (REG_BASE+0xe000)
-#define REG_UART1_CTRL   (REG_BASE+0xe004)
-#define REG_UART1_STAT   (REG_BASE+0xe008)
-#define REG_UART1_TXB    (REG_BASE+0xe00c)
-#define REG_UART1_RXB    (REG_BASE+0xe010)
-#define REG_UART1_BAUD_DIV    (REG_BASE+0xe014)
-#define REG_UART1_BAUD_CNT    (REG_BASE+0xe018)
-#define REG_UART1_BAUD_CLK    (REG_BASE+0xe01C)
-
-/********************/
-/*  Timer Register  */
-/********************/
-#define REG_TMOD	(REG_BASE+0x6000)
-#define REG_TDATA0	(REG_BASE+0x6004)
-#define REG_TDATA1	(REG_BASE+0x6008)
-#define REG_TCNT0	(REG_BASE+0x600c)
-#define REG_TCNT1	(REG_BASE+0x6010)
-
-/**********************/
-/* I/O Port Interface */
-/**********************/
-#define REG_IOPMODE	(REG_BASE+0x5000)
-#define REG_IOPCON	(REG_BASE+0x5004)
-#define REG_IOPDATA	(REG_BASE+0x5008)
-
-/*********************************/
-/* Interrupt Controller Register */
-/*********************************/
-#define REG_INTMODE     (REG_BASE+0x4000)
-#define REG_INTPEND     (REG_BASE+0x4004)
-#define REG_INTMASK     (REG_BASE+0x4008)
-
-#define REG_INTPRI0     (REG_BASE+0x400c)
-#define REG_INTPRI1	(REG_BASE+0x4010)
-#define REG_INTPRI2	(REG_BASE+0x4014)
-#define REG_INTPRI3	(REG_BASE+0x4018)
-#define REG_INTPRI4	(REG_BASE+0x401c)
-#define REG_INTPRI5	(REG_BASE+0x4020)
-#define REG_INTOFFSET	(REG_BASE+0x4024)
-#define REG_INTPNDPRI	(REG_BASE+0x4028)
-#define REG_INTPNDTST	(REG_BASE+0x402C)
-
-/*********************************/
-/* CACHE CONTROL MASKS           */
-/*********************************/
-#define CACHE_STALL      (0x00000001)
-#define CACHE_ENABLE     (0x00000002)
-#define CACHE_WRITE_BUFF (0x00000004)
-#define CACHE_MODE       (0x00000030)
-#define CACHE_MODE_00    (0x00000000)
-#define CACHE_MODE_01    (0x00000010)
-#define CACHE_MODE_10    (0x00000020)
-
-/*********************************/
-/* CACHE RAM BASE ADDRESSES      */
-/*********************************/
-#define CACHE_SET0_RAM   (0x10000000)
-#define CACHE_SET1_RAM   (0x10800000)
-#define CACHE_TAG_RAM    (0x11000000)
-
-/*********************************/
-/* CACHE_DISABLE MASK            */
-/*********************************/
-#define CACHE_DISABLE_MASK (0x04000000)
-
-#define GET_REG(reg)       (*((volatile u32 *)(reg)))
-#define PUT_REG(reg, val)  (*((volatile u32 *)(reg)) = ((u32)(val)))
-#define SET_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) |  mask))
-#define CLR_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) & ~mask))
-#define PUT_U16(reg, val)  (*((volatile u16 *)(reg)) = ((u16)(val)))
-#define PUT__U8(reg, val)  (*((volatile u8  *)(reg)) = (( u8)((val)&0xFF)))
-#define GET__U8(reg)       (*((volatile u8  *)(reg)))
-
-#define PUT_LED(val)       (PUT_REG(REG_IOPDATA, (~val)&0xFF))
-#define GET_LED()          ((~GET_REG( REG_IOPDATA)) & 0xFF)
-#define SET_LED(val)       { u32 led = GET_LED(); led |= 1 << (val);  PUT_LED( led); }
-#define CLR_LED(val)       { u32 led = GET_LED(); led &= ~(1 << (val));  PUT_LED( led); }
-
-/***********************************/
-/* CLOCK CONSTANTS -- 50 MHz Clock */
-/***********************************/
-
-#define CLK_FREQ_MHZ       (50)
-#define t_data_us(t)       ((t)*CLK_FREQ_MHZ-1)   /* t is time tick,unit[us] */
-#define t_data_ms(t)       (t_data_us((t)*1000))  /* t is time tick,unit[ms] */
-
-/*********************************************************/
-/*	       TIMER MODE REGISTER                       */
-/*********************************************************/
-#define  TM0_RUN      0x01  /* Timer 0 enable */
-#define  TM0_TOGGLE   0x02  /* 0, interval mode */
-#define  TM0_OUT_1    0x04  /* Timer 0 Initial TOUT0 value */
-#define  TM1_RUN      0x08  /* Timer 1 enable */
-#define  TM1_TOGGLE   0x10  /* 0, interval mode */
-#define  TM1_OUT_1    0x20  /* Timer 0 Initial TOUT0 value */
-
-
-/*********************************/
-/* INTERRUPT SOURCES             */
-/*********************************/
-#define INT_EXTINT0	0
-#define INT_EXTINT1	1
-#define INT_EXTINT2	2
-#define INT_EXTINT3	3
-#define INT_UARTTX0	4
-#define INT_UARTRX0	5
-#define INT_UARTTX1	6
-#define INT_UARTRX1	7
-#define INT_GDMA0	8
-#define INT_GDMA1	9
-#define INT_TIMER0	10
-#define INT_TIMER1	11
-#define INT_HDLCTXA	12
-#define INT_HDLCRXA	13
-#define INT_HDLCTXB	14
-#define INT_HDLCRXB	15
-#define INT_BDMATX	16
-#define INT_BDMARX	17
-#define INT_MACTX	18
-#define INT_MACRX	19
-#define INT_IIC		20
-#define INT_GLOBAL	21
-#define N_IRQS         (21)
-
-#ifndef __ASSEMBLER__
-struct _irq_handler {
-	void                *m_data;
-	void (*m_func)( void *data);
-};
-
-#endif
-
-#endif /* __S3C4510_h */
diff --git a/arch/arm/include/asm/arch-lpc2292/hardware.h b/arch/arm/include/asm/arch-tegra20/spl.h
index 5e227e3..5e453c5 100644
--- a/arch/arm/include/asm/arch-lpc2292/hardware.h
+++ b/arch/arm/include/asm/arch-tegra20/spl.h
@@ -1,9 +1,6 @@
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
 /*
- * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
- * Curt Brune <curt@cucy.com>
+ * (C) Copyright 2012
+ * NVIDIA Corporation <www.nvidia.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -15,7 +12,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -23,11 +20,9 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_ARCH_SPL_H_
 
-#if defined(CONFIG_LPC2292)
-#include <asm/arch-lpc2292/lpc2292_registers.h>
-#else
-#error No hardware file defined for this configuration
-#endif
+#define BOOT_DEVICE_RAM         1
 
-#endif /* __ASM_ARCH_HARDWARE_H */
+#endif
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index f8088fe..2b9af93 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -34,7 +34,7 @@
 typedef	struct	global_data {
 	bd_t		*bd;
 	unsigned long	flags;
-	unsigned long	baudrate;
+	unsigned int	baudrate;
 	unsigned long	have_console;	/* serial_init() was called */
 #ifdef CONFIG_PRE_CONSOLE_BUFFER
 	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
index 89df4dc..78a7fac 100644
--- a/arch/arm/include/asm/setup.h
+++ b/arch/arm/include/asm/setup.h
@@ -267,3 +267,8 @@ struct meminfo {
 extern struct meminfo meminfo;
 
 #endif
+
+/*
+ * Board specified tags
+ */
+void setup_board_tags(struct tag **in_params);
diff --git a/arch/arm/include/asm/u-boot.h b/arch/arm/include/asm/u-boot.h
index eac3800..2ba98bc 100644
--- a/arch/arm/include/asm/u-boot.h
+++ b/arch/arm/include/asm/u-boot.h
@@ -37,7 +37,7 @@
 #define _U_BOOT_H_	1
 
 typedef struct bd_info {
-    int			bi_baudrate;	/* serial console baudrate */
+	unsigned int	bi_baudrate;	/* serial console baudrate */
     ulong	        bi_arch_number;	/* unique id for this board */
     ulong	        bi_boot_params;	/* where this board expects params */
 	unsigned long	bi_arm_freq; /* arm frequency */
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index 0b47ab3..92cad9a 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -57,13 +57,6 @@
 #include <miiphy.h>
 #endif
 
-#ifdef CONFIG_DRIVER_SMC91111
-#include "../drivers/net/smc91111.h"
-#endif
-#ifdef CONFIG_DRIVER_LAN91C96
-#include "../drivers/net/lan91c96.h"
-#endif
-
 DECLARE_GLOBAL_DATA_PTR;
 
 ulong monitor_flash_len;
@@ -274,6 +267,8 @@ void board_init_f(ulong bootflag)
 #ifdef CONFIG_PRAM
 	ulong reg;
 #endif
+	void *new_fdt = NULL;
+	size_t fdt_size = 0;
 
 	bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
 
@@ -409,6 +404,22 @@ void board_init_f(ulong bootflag)
 	debug("Reserving %zu Bytes for Global Data at: %08lx\n",
 			sizeof (gd_t), addr_sp);
 
+#if defined(CONFIG_OF_SEPARATE) && defined(CONFIG_OF_CONTROL)
+	/*
+	 * If the device tree is sitting immediate above our image then we
+	 * must relocate it. If it is embedded in the data section, then it
+	 * will be relocated with other data.
+	 */
+	if (gd->fdt_blob) {
+		fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
+
+		addr_sp -= fdt_size;
+		new_fdt = (void *)addr_sp;
+		debug("Reserving %zu Bytes for FDT at: %08lx\n",
+		      fdt_size, addr_sp);
+	}
+#endif
+
 	/* setup stackpointer for exeptions */
 	gd->irq_sp = addr_sp;
 #ifdef CONFIG_USE_IRQ
@@ -442,6 +453,10 @@ void board_init_f(ulong bootflag)
 	gd->start_addr_sp = addr_sp;
 	gd->reloc_off = addr - _TEXT_BASE;
 	debug("relocation Offset is: %08lx\n", gd->reloc_off);
+	if (new_fdt) {
+		memcpy(new_fdt, gd->fdt_blob, fdt_size);
+		gd->fdt_blob = new_fdt;
+	}
 	memcpy(id, (void *)gd, sizeof(gd_t));
 
 	relocate_code(addr_sp, id, addr);
@@ -591,16 +606,6 @@ void board_init_r(gd_t *id, ulong dest_addr)
 	/* enable exceptions */
 	enable_interrupts();
 
-	/* Perform network card initialisation if necessary */
-#if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96)
-	/* XXX: this needs to be moved to board init */
-	if (getenv("ethaddr")) {
-		uchar enetaddr[6];
-		eth_getenv_enetaddr("ethaddr", enetaddr);
-		smc_set_mac_addr(enetaddr);
-	}
-#endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */
-
 	/* Initialize from environment */
 	load_addr = getenv_ulong("loadaddr", 16, load_addr);
 
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 37476cc..1bd2730 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -34,6 +34,7 @@
 #include <libfdt.h>
 #include <fdt_support.h>
 #include <asm/bootm.h>
+#include <linux/compiler.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -269,6 +270,8 @@ static int create_fdt(bootm_headers_t *images)
 }
 #endif
 
+__weak void setup_board_tags(struct tag **in_params) {}
+
 /* Subcommand: PREP */
 static void boot_prep_linux(bootm_headers_t *images)
 {
@@ -310,6 +313,7 @@ static void boot_prep_linux(bootm_headers_t *images)
 			setup_initrd_tag(gd->bd, images->rd_start,
 			images->rd_end);
 #endif
+		setup_board_tags(&params);
 		setup_end_tag(gd->bd);
 #else /* all tags */
 		printf("FDT and ATAGS support not compiled in - hanging\n");