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authorSimon Glass <sjg@chromium.org>2012-12-13 20:48:39 +0000
committerTom Rini <trini@ti.com>2013-02-01 15:21:58 -0500
commit34fd5d253dee74fa8e431fc2183aa9f2637afa04 (patch)
tree35ee1ba256a3c5b7f4ca512b9c58b3b922ef8a05 /arch/arm
parent37434783bbc3a16658abdaec357ad9d9310947d2 (diff)
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arm: Move tlb_addr and tlb_size to arch_global_data
Move these fields into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Address tlb_size in this patch as well] Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/include/asm/global_data.h8
-rw-r--r--arch/arm/lib/board.c8
-rw-r--r--arch/arm/lib/cache-cp15.c6
3 files changed, 11 insertions, 11 deletions
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 5d414ef..0c1dbe8 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -44,6 +44,10 @@ struct arch_global_data {
#ifdef CONFIG_IXP425
unsigned long timestamp;
#endif
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+ unsigned long tlb_addr;
+ unsigned long tlb_size;
+#endif
};
/*
@@ -74,10 +78,6 @@ typedef struct global_data {
unsigned long irq_sp; /* irq stack pointer */
unsigned long start_addr_sp; /* start_addr_stackpointer */
unsigned long reloc_off;
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
- unsigned long tlb_addr;
- unsigned long tlb_size;
-#endif
const void *fdt_blob; /* Our device tree, NULL if none */
void **jt; /* jump table */
char env_buf[32]; /* buffer for getenv() before reloc. */
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index 9f861cc..162e2cc 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -355,14 +355,14 @@ void board_init_f(ulong bootflag)
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
/* reserve TLB table */
- gd->tlb_size = 4096 * 4;
- addr -= gd->tlb_size;
+ gd->arch.tlb_size = 4096 * 4;
+ addr -= gd->arch.tlb_size;
/* round down to next 64 kB limit */
addr &= ~(0x10000 - 1);
- gd->tlb_addr = addr;
- debug("TLB table from %08lx to %08lx\n", addr, addr + gd->tlb_size);
+ gd->arch.tlb_addr = addr;
+ debug("TLB table from %08lx to %08lx\n", addr, addr + gd->arch.tlb_size);
#endif
/* round down to next 4 kB limit */
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 1cab27c..b6e5e95 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -46,7 +46,7 @@ static void cp_delay (void)
void set_section_dcache(int section, enum dcache_option option)
{
- u32 *page_table = (u32 *)gd->tlb_addr;
+ u32 *page_table = (u32 *)gd->arch.tlb_addr;
u32 value;
value = (section << MMU_SECTION_SHIFT) | (3 << 10);
@@ -65,7 +65,7 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop)
void mmu_set_region_dcache_behaviour(u32 start, int size,
enum dcache_option option)
{
- u32 *page_table = (u32 *)gd->tlb_addr;
+ u32 *page_table = (u32 *)gd->arch.tlb_addr;
u32 upto, end;
end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
@@ -111,7 +111,7 @@ static inline void mmu_setup(void)
/* Copy the page table address to cp15 */
asm volatile("mcr p15, 0, %0, c2, c0, 0"
- : : "r" (gd->tlb_addr) : "memory");
+ : : "r" (gd->arch.tlb_addr) : "memory");
/* Set the access control to all-supervisor */
asm volatile("mcr p15, 0, %0, c3, c0, 0"
: : "r" (~0));