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authorAndreas Müller <schnitzeltony@gmx.de>2012-01-04 15:26:25 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-01-16 08:40:13 +0100
commit137703b811502dfea364650fb3e17f20b4c21333 (patch)
tree40d0808c67ee5cbf308e481449dc78effbbffcfc /arch/arm
parent761ca31e47e483a0c0c66894ead1a2d0db37b314 (diff)
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overo: add SPL support
* implementation based on ti beagleboard/omap3evm * timing data and i2c workaround for revision 0 boards taken from x-loader * run-tested with overo revision 0 and 1 / boot from NAND and SDcard * run-tested with x-loader Signed-off-by: Andreas Müller <schnitzeltony@gmx.de> Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/include/asm/arch-omap3/mem.h26
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
index 5fd02d4..4ca929e 100644
--- a/arch/arm/include/asm/arch-omap3/mem.h
+++ b/arch/arm/include/asm/arch-omap3/mem.h
@@ -123,6 +123,32 @@ enum {
V_MCFG_BANKALLOCATION_RBC | \
V_MCFG_B32NOT16_32 | V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR
+/* Hynix part of Overo (165MHz optimized) 6.06ns */
+#define HYNIX_TDAL_165 6
+#define HYNIX_TDPL_165 3
+#define HYNIX_TRRD_165 2
+#define HYNIX_TRCD_165 3
+#define HYNIX_TRP_165 3
+#define HYNIX_TRAS_165 7
+#define HYNIX_TRC_165 10
+#define HYNIX_TRFC_165 21
+#define HYNIX_V_ACTIMA_165 \
+ ACTIM_CTRLA(HYNIX_TRFC_165, HYNIX_TRC_165, \
+ HYNIX_TRAS_165, HYNIX_TRP_165, \
+ HYNIX_TRCD_165, HYNIX_TRRD_165, \
+ HYNIX_TDPL_165, HYNIX_TDAL_165)
+
+#define HYNIX_TWTR_165 1
+#define HYNIX_TCKE_165 1
+#define HYNIX_TXP_165 2
+#define HYNIX_XSR_165 24
+#define HYNIX_V_ACTIMB_165 \
+ ACTIM_CTRLB(HYNIX_TWTR_165, HYNIX_TCKE_165, \
+ HYNIX_TXP_165, HYNIX_XSR_165)
+
+#define HYNIX_RASWIDTH_165 0x2
+#define HYNIX_V_MCFG_165(size) MCFG((size), HYNIX_RASWIDTH_165)
+
/* Hynix part of AM/DM37xEVM (200MHz optimized) */
#define HYNIX_TDAL_200 6
#define HYNIX_TDPL_200 3