Merge branch 'u-boot/master'

Conflicts:
	drivers/net/Makefile

(trivial merge)

3 files changed, 155 insertions, 82 deletions

diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
index b2d30b1..35d8d38 100644
--- a/arch/arm/cpu/Makefile
+++ b/arch/arm/cpu/Makefile
@@ -1,3 +1,6 @@
 obj-$(CONFIG_AT91FAMILY) += at91-common/
-obj-$(CONFIG_TEGRA) += $(SOC)-common/
+obj-$(CONFIG_TEGRA20) += tegra20-common/
+obj-$(CONFIG_TEGRA30) += tegra30-common/
+obj-$(CONFIG_TEGRA114) += tegra114-common/
+obj-$(CONFIG_TEGRA124) += tegra124-common/
 obj-$(CONFIG_TEGRA) += tegra-common/
diff --git a/arch/arm/cpu/tegra20-common/crypto.c b/arch/arm/cpu/tegra20-common/crypto.c
index 8209f76..ec95d7c 100644
--- a/arch/arm/cpu/tegra20-common/crypto.c
+++ b/arch/arm/cpu/tegra20-common/crypto.c
@@ -19,74 +19,6 @@ enum security_op {
 	SECURITY_ENCRYPT	= 1 << 1,	/* Encrypt the data */
 };
 
-static void debug_print_vector(char *name, u32 num_bytes, u8 *data)
-{
-	u32 i;
-
-	debug("%s [%d] @0x%08x", name, num_bytes, (u32)data);
-	for (i = 0; i < num_bytes; i++) {
-		if (i % 16 == 0)
-			debug(" = ");
-		debug("%02x", data[i]);
-		if ((i+1) % 16 != 0)
-			debug(" ");
-	}
-	debug("\n");
-}
-
-/**
- * Apply chain data to the destination using EOR
- *
- * Each array is of length AES_AES_KEY_LENGTH.
- *
- * \param cbc_chain_data	Chain data
- * \param src			Source data
- * \param dst			Destination data, which is modified here
- */
-static void apply_cbc_chain_data(u8 *cbc_chain_data, u8 *src, u8 *dst)
-{
-	int i;
-
-	for (i = 0; i < 16; i++)
-		*dst++ = *src++ ^ *cbc_chain_data++;
-}
-
-/**
- * Encrypt some data with AES.
- *
- * \param key_schedule		Expanded key to use
- * \param src			Source data to encrypt
- * \param dst			Destination buffer
- * \param num_aes_blocks	Number of AES blocks to encrypt
- */
-static void encrypt_object(u8 *key_schedule, u8 *src, u8 *dst,
-			   u32 num_aes_blocks)
-{
-	u8 tmp_data[AES_KEY_LENGTH];
-	u8 *cbc_chain_data;
-	u32 i;
-
-	cbc_chain_data = zero_key;	/* Convenient array of 0's for IV */
-
-	for (i = 0; i < num_aes_blocks; i++) {
-		debug("encrypt_object: block %d of %d\n", i, num_aes_blocks);
-		debug_print_vector("AES Src", AES_KEY_LENGTH, src);
-
-		/* Apply the chain data */
-		apply_cbc_chain_data(cbc_chain_data, src, tmp_data);
-		debug_print_vector("AES Xor", AES_KEY_LENGTH, tmp_data);
-
-		/* encrypt the AES block */
-		aes_encrypt(tmp_data, key_schedule, dst);
-		debug_print_vector("AES Dst", AES_KEY_LENGTH, dst);
-
-		/* Update pointers for next loop. */
-		cbc_chain_data = dst;
-		src += AES_KEY_LENGTH;
-		dst += AES_KEY_LENGTH;
-	}
-}
-
 /**
  * Shift a vector left by one bit
  *
@@ -129,39 +61,31 @@ static void sign_object(u8 *key, u8 *key_schedule, u8 *src, u8 *dst,
 	for (i = 0; i < AES_KEY_LENGTH; i++)
 		tmp_data[i] = 0;
 
-	encrypt_object(key_schedule, tmp_data, left, 1);
-	debug_print_vector("AES(key, nonce)", AES_KEY_LENGTH, left);
+	aes_cbc_encrypt_blocks(key_schedule, tmp_data, left, 1);
 
 	left_shift_vector(left, k1, sizeof(left));
-	debug_print_vector("L", AES_KEY_LENGTH, left);
 
 	if ((left[0] >> 7) != 0) /* get MSB of L */
 		k1[AES_KEY_LENGTH-1] ^= AES_CMAC_CONST_RB;
-	debug_print_vector("K1", AES_KEY_LENGTH, k1);
 
 	/* compute the AES-CMAC value */
 	for (i = 0; i < num_aes_blocks; i++) {
 		/* Apply the chain data */
-		apply_cbc_chain_data(cbc_chain_data, src, tmp_data);
+		aes_apply_cbc_chain_data(cbc_chain_data, src, tmp_data);
 
 		/* for the final block, XOR K1 into the IV */
 		if (i == num_aes_blocks - 1)
-			apply_cbc_chain_data(tmp_data, k1, tmp_data);
+			aes_apply_cbc_chain_data(tmp_data, k1, tmp_data);
 
 		/* encrypt the AES block */
 		aes_encrypt(tmp_data, key_schedule, dst);
 
 		debug("sign_obj: block %d of %d\n", i, num_aes_blocks);
-		debug_print_vector("AES-CMAC Src", AES_KEY_LENGTH, src);
-		debug_print_vector("AES-CMAC Xor", AES_KEY_LENGTH, tmp_data);
-		debug_print_vector("AES-CMAC Dst", AES_KEY_LENGTH, dst);
 
 		/* Update pointers for next loop. */
 		cbc_chain_data = dst;
 		src += AES_KEY_LENGTH;
 	}
-
-	debug_print_vector("AES-CMAC Hash", AES_KEY_LENGTH, dst);
 }
 
 /**
@@ -180,7 +104,6 @@ static int encrypt_and_sign(u8 *key, enum security_op oper, u8 *src,
 	u8 key_schedule[AES_EXPAND_KEY_LENGTH];
 
 	debug("encrypt_and_sign: length = %d\n", length);
-	debug_print_vector("AES key", AES_KEY_LENGTH, key);
 
 	/*
 	 * The only need for a key is for signing/checksum purposes, so
@@ -193,7 +116,7 @@ static int encrypt_and_sign(u8 *key, enum security_op oper, u8 *src,
 	if (oper & SECURITY_ENCRYPT) {
 		/* Perform this in place, resulting in src being encrypted. */
 		debug("encrypt_and_sign: begin encryption\n");
-		encrypt_object(key_schedule, src, src, num_aes_blocks);
+		aes_cbc_encrypt_blocks(key_schedule, src, src, num_aes_blocks);
 		debug("encrypt_and_sign: end encryption\n");
 	}
 
diff --git a/arch/arm/include/asm/arch-rmobile/ehci-rmobile.h b/arch/arm/include/asm/arch-rmobile/ehci-rmobile.h
new file mode 100644
index 0000000..463654e
--- /dev/null
+++ b/arch/arm/include/asm/arch-rmobile/ehci-rmobile.h
@@ -0,0 +1,147 @@
+/*
+ *  Copyright (C) 2013,2014 Renesas Electronics Corporation
+ *  Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ *  SPDX-License-Identifier:     GPL-2.0
+ */
+
+#ifndef __EHCI_RMOBILE_H__
+#define __EHCI_RMOBILE_H__
+
+/* Register offset */
+#define OHCI_OFFSET	0x00
+#define OHCI_SIZE	0x1000
+#define EHCI_OFFSET	0x1000
+#define EHCI_SIZE	0x1000
+
+#define EHCI_USBCMD	(EHCI_OFFSET + 0x0020)
+
+/* USBCTR */
+#define DIRPD		(1 << 8)
+#define PLL_RST		(1 << 2)
+#define PCICLK_MASK	(1 << 1)
+#define USBH_RST	(1 << 0)
+
+/* CMND_STS */
+#define SERREN		(1 << 8)
+#define PERREN		(1 << 6)
+#define MASTEREN	(1 << 2)
+#define MEMEN		(1 << 1)
+
+/* PCIAHB_WIN1_CTR and PCIAHB_WIN2_CTR */
+#define PCIAHB_WIN_PREFETCH	((1 << 1)|(1 << 0))
+
+/* AHBPCI_WIN1_CTR */
+#define PCIWIN1_PCICMD		((1 << 3)|(1 << 1))
+#define AHB_CFG_AHBPCI		0x40000000
+#define AHB_CFG_HOST		0x80000000
+
+/* AHBPCI_WIN2_CTR */
+#define PCIWIN2_PCICMD		((1 << 2)|(1 << 1))
+
+/* PCI_INT_ENABLE */
+#define USBH_PMEEN		(1 << 19)
+#define USBH_INTBEN		(1 << 17)
+#define USBH_INTAEN		(1 << 16)
+
+/* AHB_BUS_CTR */
+#define SMODE_READY_CTR		(1 << 17)
+#define SMODE_READ_BURST	(1 << 16)
+#define MMODE_HBUSREQ		(1 << 7)
+#define MMODE_BOUNDARY		((1 << 6)|(1 << 5))
+#define MMODE_BURST_WIDTH	((1 << 4)|(1 << 3))
+#define MMODE_SINGLE_MODE	((1 << 4)|(1 << 3))
+#define MMODE_WR_INCR		(1 << 2)
+#define MMODE_BYTE_BURST	(1 << 1)
+#define MMODE_HTRANS		(1 << 0)
+
+/* PCI_ARBITER_CTR */
+#define PCIBUS_PARK_TIMER       0x00FF0000
+#define PCIBUS_PARK_TIMER_SET   0x00070000
+#define PCIBP_MODE		(1 << 12)
+#define PCIREQ7                 (1 << 7)
+#define PCIREQ6                 (1 << 6)
+#define PCIREQ5                 (1 << 5)
+#define PCIREQ4                 (1 << 4)
+#define PCIREQ3                 (1 << 3)
+#define PCIREQ2                 (1 << 2)
+#define PCIREQ1                 (1 << 1)
+#define PCIREQ0                 (1 << 0)
+
+#define SMSTPCR7        0xE615014C
+#define SMSTPCR703      (1 << 3)
+
+/* Init AHB master and slave functions of the host logic */
+#define AHB_BUS_CTR_INIT \
+	(SMODE_READY_CTR | MMODE_HBUSREQ | MMODE_WR_INCR | \
+	 MMODE_BYTE_BURST | MMODE_HTRANS)
+
+#define USBCTR_WIN_SIZE_1GB	0x800
+
+/* PCI Configuration Registers */
+#define PCI_CONF_OHCI_OFFSET	0x10000
+#define PCI_CONF_EHCI_OFFSET	0x10100
+struct ahb_pciconf {
+	u32 vid_did;
+	u32 cmnd_sts;
+	u32 rev;
+	u32 cache_line;
+	u32 basead;
+};
+
+/* PCI Configuration Registers for AHB-PCI Bridge Registers */
+#define PCI_CONF_AHBPCI_OFFSET	0x10000
+struct ahbconf_pci_bridge {
+	u32 vid_did;		/* 0x00 */
+	u32 cmnd_sts;
+	u32 revid_cc;
+	u32 cls_lt_ht_bist;
+	u32 basead;		/* 0x10 */
+	u32 win1_basead;
+	u32 win2_basead;
+	u32 dummy0[5];
+	u32 ssvdi_ssid;		/* 0x2C */
+	u32 dummy1[4];
+	u32 intr_line_pin;
+};
+
+/* AHB-PCI Bridge PCI Communication Registers */
+#define AHBPCI_OFFSET	0x10800
+struct ahbcom_pci_bridge {
+	u32 pciahb_win1_ctr;	/* 0x00 */
+	u32 pciahb_win2_ctr;
+	u32 pciahb_dct_ctr;
+	u32 dummy0;
+	u32 ahbpci_win1_ctr;	/* 0x10 */
+	u32 ahbpci_win2_ctr;
+	u32 dummy1;
+	u32 ahbpci_dct_ctr;
+	u32 pci_int_enable;	/* 0x20 */
+	u32 pci_int_status;
+	u32 dummy2[2];
+	u32 ahb_bus_ctr;	/* 0x30 */
+	u32 usbctr;
+	u32 dummy3[2];
+	u32 pci_arbiter_ctr;	/* 0x40 */
+	u32 dummy4;
+	u32 pci_unit_rev;	/* 0x48 */
+};
+
+struct rmobile_ehci_reg {
+	u32 hciversion;		/* hciversion/caplength */
+	u32 hcsparams;		/* hcsparams */
+	u32 hccparams;		/* hccparams */
+	u32 hcsp_portroute;	/* hcsp_portroute */
+	u32 usbcmd;		/* usbcmd */
+	u32 usbsts;		/* usbsts */
+	u32 usbintr;		/* usbintr */
+	u32 frindex;		/* frindex */
+	u32 ctrldssegment;	/* ctrldssegment */
+	u32 periodiclistbase;	/* periodiclistbase */
+	u32 asynclistaddr;	/* asynclistaddr */
+	u32 dummy[9];
+	u32 configflag;		/* configflag */
+	u32 portsc;		/* portsc */
+};
+
+#endif /* __EHCI_RMOBILE_H__ */