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authorBenoît Thébaudeau <benoit.thebaudeau@advansee.com>2012-08-14 10:32:54 +0000
committerStefano Babic <sbabic@denx.de>2012-09-06 11:04:41 +0200
commite7619554173a9d9f72dc19f97a804afea135f07f (patch)
treed6aa05579f294e0dffc65e05b12792adf5900bf7 /arch/arm
parent0d7d3830984012a8209bbf497f92add652082afb (diff)
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mx35: Fix decode_pll
The MFN bit-field of the PLL registers represents a signed value. See the reference manual. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/cpu/arm1136/mx35/generic.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c
index d435e8a..de7503c 100644
--- a/arch/arm/cpu/arm1136/mx35/generic.c
+++ b/arch/arm/cpu/arm1136/mx35/generic.c
@@ -24,6 +24,7 @@
*/
#include <common.h>
+#include <div64.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/imx-regs.h>
@@ -129,15 +130,17 @@ static int get_ahb_div(u32 pdr0)
static u32 decode_pll(u32 reg, u32 infreq)
{
u32 mfi = (reg >> 10) & 0xf;
- u32 mfn = reg & 0x3f;
- u32 mfd = (reg >> 16) & 0x3f;
+ s32 mfn = reg & 0x3ff;
+ u32 mfd = (reg >> 16) & 0x3ff;
u32 pd = (reg >> 26) & 0xf;
mfi = mfi <= 5 ? 5 : mfi;
+ mfn = mfn >= 512 ? mfn - 1024 : mfn;
mfd += 1;
pd += 1;
- return ((2 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
+ return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
+ mfd * pd);
}
static u32 get_mcu_main_clk(void)