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authorFabio Estevam <fabio.estevam@freescale.com>2014-08-15 00:24:29 -0300
committerStefano Babic <sbabic@denx.de>2014-08-20 13:15:23 +0200
commitd145878d59c80a44d8c6e6d606b898ab87d205ee (patch)
tree771df21563a4e8bbce7195e25b5dc53e352014d4 /arch/arm
parent5c045cddaa2411aba856bad5245ee0e0654569c2 (diff)
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mx6sxsabresd: Add Ethernet support
mx6sxsabresd board has 2 FEC ports, each one connected to a AR8031. Add support for one FEC port initially. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/include/asm/arch-mx6/crm_regs.h1
-rw-r--r--arch/arm/include/asm/arch-mx6/iomux.h10
2 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 9a7fb34..e67b5b9 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -981,6 +981,7 @@ struct mxc_ccm_reg {
#define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000
#define BF_ANADIG_PLL_ENET_RSVD1(v) \
(((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1)
+#define BM_ANADIG_PLL_ENET_REF_25M_ENABLE 0x00200000
#define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000
#define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000
#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h
index 6a4a632..f54db69 100644
--- a/arch/arm/include/asm/arch-mx6/iomux.h
+++ b/arch/arm/include/asm/arch-mx6/iomux.h
@@ -65,6 +65,16 @@
#define IOMUX_GPR1_FEC_MASK (IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK \
| IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK)
+#define IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK (0x1 << 17)
+#define IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK (0x1 << 13)
+#define IOMUX_GPR1_FEC1_MASK (IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK \
+ | IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK)
+
+#define IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK (0x1 << 18)
+#define IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK (0x1 << 14)
+#define IOMUX_GPR1_FEC2_MASK (IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK \
+ | IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK)
+
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0<<24)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (1<<24)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (2<<24)