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authorXiubo Li <Li.Xiubo@freescale.com>2014-11-21 17:40:56 +0800
committerYork Sun <yorksun@freescale.com>2014-12-11 09:41:53 -0800
commit290e6e921f255fdee072d21539bbad16b9a3e714 (patch)
tree37eb3c3e98bf2a03db559b805d8ce40e0f8c4a2f /arch/arm
parent73a1cb27c0d9e93d97cd7a344fd341f638ba3a2a (diff)
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ls1021a: adding a secondary core boot address and kick functions
Define the board specific smp_set_cpu_boot_addr() function to set the start address for secondary cores in the LS1021A specific manner. Define the board specific smp_kick_all_cpus() functioin to boot a secondary core. Here the BRR contains control bits for enabling boot for each core. On exiting HRESET or PORESET, the RCW BOOT_HO field optionally allows for logical core 0 to be released for booting or to remain in boot holdoff. All other cores remain in boot holdoff until their corresponding bit is set. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/cpu/armv7/ls102xa/cpu.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index fae6c68..ce2d92f 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -117,3 +117,21 @@ int arch_cpu_init(void)
return 0;
}
+
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+/* Set the address at which the secondary core starts from.*/
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+ out_be32(&gur->scratchrw[0], addr);
+}
+
+/* Release the secondary core from holdoff state and kick it */
+void smp_kick_all_cpus(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+ out_be32(&gur->brrl, 0x2);
+}
+#endif