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| author | Aneesh V <aneesh@ti.com> | 2011-08-11 04:35:45 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-09-04 11:36:16 +0200 |
| commit | cabe2878a8201441a8aa4c482acb568f9ca137f0 (patch) | |
| tree | b18d2af9ba2fdd04498554fb6db12a7d9b4a2de4 /arch/arm | |
| parent | 882f80b993f3719cce5bfa7f1bca9b1b23062b5f (diff) | |
| download | u-boot-imx-cabe2878a8201441a8aa4c482acb568f9ca137f0.zip u-boot-imx-cabe2878a8201441a8aa4c482acb568f9ca137f0.tar.gz u-boot-imx-cabe2878a8201441a8aa4c482acb568f9ca137f0.tar.bz2 | |
armv7: cache: remove flush on un-aligned invalidate
Remove the flush of boundary cache-lines done as part
of invalidate on a non cache-line boundary aligned
buffer
Also, print a warning when this situation is recognized.
Signed-off-by: Aneesh V <aneesh@ti.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/armv7/cache_v7.c | 14 | ||||
| -rw-r--r-- | arch/arm/lib/cache-pl310.c | 15 |
2 files changed, 17 insertions, 12 deletions
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 665f025..1b4e808 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -181,21 +181,23 @@ static void v7_dcache_inval_range(u32 start, u32 stop, u32 line_len) u32 mva; /* - * If start address is not aligned to cache-line flush the first - * line to prevent affecting somebody else's buffer + * If start address is not aligned to cache-line do not + * invalidate the first cache-line */ if (start & (line_len - 1)) { - v7_dcache_clean_inval_range(start, start + 1, line_len); + printf("ERROR: %s - start address is not aligned - 0x%08x\n", + __func__, start); /* move to next cache line */ start = (start + line_len - 1) & ~(line_len - 1); } /* - * If stop address is not aligned to cache-line flush the last - * line to prevent affecting somebody else's buffer + * If stop address is not aligned to cache-line do not + * invalidate the last cache-line */ if (stop & (line_len - 1)) { - v7_dcache_clean_inval_range(stop, stop + 1, line_len); + printf("ERROR: %s - stop address is not aligned - 0x%08x\n", + __func__, stop); /* align to the beginning of this cache line */ stop &= ~(line_len - 1); } diff --git a/arch/arm/lib/cache-pl310.c b/arch/arm/lib/cache-pl310.c index 36c629c..21d13f7 100644 --- a/arch/arm/lib/cache-pl310.c +++ b/arch/arm/lib/cache-pl310.c @@ -26,6 +26,7 @@ #include <asm/armv7.h> #include <asm/pl310.h> #include <config.h> +#include <common.h> struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; @@ -89,21 +90,23 @@ void v7_outer_cache_inval_range(u32 start, u32 stop) u32 pa, line_size = 32; /* - * If start address is not aligned to cache-line flush the first - * line to prevent affecting somebody else's buffer + * If start address is not aligned to cache-line do not + * invalidate the first cache-line */ if (start & (line_size - 1)) { - v7_outer_cache_flush_range(start, start + 1); + printf("ERROR: %s - start address is not aligned - 0x%08x\n", + __func__, start); /* move to next cache line */ start = (start + line_size - 1) & ~(line_size - 1); } /* - * If stop address is not aligned to cache-line flush the last - * line to prevent affecting somebody else's buffer + * If stop address is not aligned to cache-line do not + * invalidate the last cache-line */ if (stop & (line_size - 1)) { - v7_outer_cache_flush_range(stop, stop + 1); + printf("ERROR: %s - stop address is not aligned - 0x%08x\n", + __func__, stop); /* align to the beginning of this cache line */ stop &= ~(line_size - 1); } |