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authorSandor Yu <R01008@freescale.com>2014-07-04 17:13:58 +0800
committerSandor Yu <R01008@freescale.com>2014-07-07 10:05:28 +0800
commitc83fd326e810c2fff44b8b02e78406d5d04c977c (patch)
treea28b81c0c71d6c339eff812a56087ad0bd08f0bf /arch/arm
parent4ca9535c91c40da93703bd20727700cd33994f93 (diff)
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ENGR00321299 gis: clean csi0 input mux set bit in GPR
When gis enable in uboot, the CSI0 input mux select setting to vadc module, clean the bit when gis disabled. Signed-off-by: Sandor Yu <R01008@freescale.com> (cherry picked from commit ae66b17b7da3be50dc81ca636b67e8e879f52e26)
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 189463d..1f870d6 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -413,6 +413,7 @@ void vadc_power_up(void)
void vadc_power_down(void)
{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_GPR_BASE_ADDR;
u32 val;
/* Power down vadc ext power
@@ -421,6 +422,11 @@ void vadc_power_down(void)
val &= ~0x40000;
val |= 0x20000;
writel(val, GPC_BASE_ADDR + 0);
+
+ /* clean csi0 connect to vadc */
+ val = readl(&iomux->gpr[5]);
+ val &= ~IMX6SX_GPR5_CSI1_MUX_CTRL_MASK,
+ writel(val, &iomux->gpr[5]);
}
#endif