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authorStefan Roese <sr@denx.de>2013-04-09 21:06:08 +0000
committerStefano Babic <sbabic@denx.de>2013-04-22 10:23:42 +0200
commit8870e4599689a879051f945c97551309d23ff176 (patch)
tree0163e2aa03934e1f78e22f47773d35ce11ecdb53 /arch/arm
parent0499218dbcc30532bcc1b7b2ee44b8876675bced (diff)
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imx: Move some i.MX common functions into the imx-common directory
This patch moves the following functions into the imx-common directory: - mxs_wait_mask_set() - mxs_wait_mask_clr() - mxs_reset_block() These are currently used by i.MX28. But the upcoming GPMI NAND port for i.MX6 will also use these functions. So lets move them to a common location to re-use them. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/mxs.c63
-rw-r--r--arch/arm/imx-common/Makefile3
-rw-r--r--arch/arm/imx-common/misc.c84
-rw-r--r--arch/arm/include/asm/arch-mx6/sys_proto.h10
4 files changed, 97 insertions, 63 deletions
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c
index 6616f4e..a5e388b 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxs.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -39,12 +39,6 @@
DECLARE_GLOBAL_DATA_PTR;
-/* 1 second delay should be plenty of time for block reset. */
-#define RESET_MAX_TIMEOUT 1000000
-
-#define MXS_BLOCK_SFTRST (1 << 31)
-#define MXS_BLOCK_CLKGATE (1 << 30)
-
/* Lowlevel init isn't used on i.MX28, so just have a dummy here */
inline void lowlevel_init(void) {}
@@ -82,63 +76,6 @@ void enable_caches(void)
#endif
}
-int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
- int timeout)
-{
- while (--timeout) {
- if ((readl(&reg->reg) & mask) == mask)
- break;
- udelay(1);
- }
-
- return !timeout;
-}
-
-int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
- int timeout)
-{
- while (--timeout) {
- if ((readl(&reg->reg) & mask) == 0)
- break;
- udelay(1);
- }
-
- return !timeout;
-}
-
-int mxs_reset_block(struct mxs_register_32 *reg)
-{
- /* Clear SFTRST */
- writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
-
- if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
- return 1;
-
- /* Clear CLKGATE */
- writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
-
- /* Set SFTRST */
- writel(MXS_BLOCK_SFTRST, &reg->reg_set);
-
- /* Wait for CLKGATE being set */
- if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
- return 1;
-
- /* Clear SFTRST */
- writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
-
- if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
- return 1;
-
- /* Clear CLKGATE */
- writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
-
- if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
- return 1;
-
- return 0;
-}
-
void mx28_fixup_vt(uint32_t start_addr)
{
uint32_t *vt = (uint32_t *)0x20;
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 44b6822..9309439 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -31,6 +31,9 @@ ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
COBJS-y = iomux-v3.o timer.o cpu.o speed.o
COBJS-$(CONFIG_I2C_MXC) += i2c-mxv7.o
endif
+ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
+COBJS-y += misc.o
+endif
COBJS-$(CONFIG_CMD_BMODE) += cmd_bmode.o
COBJS-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
COBJS := $(sort $(COBJS-y))
diff --git a/arch/arm/imx-common/misc.c b/arch/arm/imx-common/misc.c
new file mode 100644
index 0000000..220785c
--- /dev/null
+++ b/arch/arm/imx-common/misc.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2013 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/imx-common/regs-common.h>
+
+/* 1 second delay should be plenty of time for block reset. */
+#define RESET_MAX_TIMEOUT 1000000
+
+#define MXS_BLOCK_SFTRST (1 << 31)
+#define MXS_BLOCK_CLKGATE (1 << 30)
+
+int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
+ int timeout)
+{
+ while (--timeout) {
+ if ((readl(&reg->reg) & mask) == mask)
+ break;
+ udelay(1);
+ }
+
+ return !timeout;
+}
+
+int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
+ int timeout)
+{
+ while (--timeout) {
+ if ((readl(&reg->reg) & mask) == 0)
+ break;
+ udelay(1);
+ }
+
+ return !timeout;
+}
+
+int mxs_reset_block(struct mxs_register_32 *reg)
+{
+ /* Clear SFTRST */
+ writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
+
+ if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+ return 1;
+
+ /* Clear CLKGATE */
+ writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
+
+ /* Set SFTRST */
+ writel(MXS_BLOCK_SFTRST, &reg->reg_set);
+
+ /* Wait for CLKGATE being set */
+ if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+ return 1;
+
+ /* Clear SFTRST */
+ writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
+
+ if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+ return 1;
+
+ /* Clear CLKGATE */
+ writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
+
+ if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+ return 1;
+
+ return 0;
+}
diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
index 3193297..38e4e51 100644
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -24,6 +24,8 @@
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
+#include <asm/imx-common/regs-common.h>
+
#define MXC_CPU_MX51 0x51
#define MXC_CPU_MX53 0x53
#define MXC_CPU_MX6SL 0x60
@@ -46,4 +48,12 @@ void set_vddsoc(u32 mv);
int fecmxc_initialize(bd_t *bis);
u32 get_ahb_clk(void);
u32 get_periph_clk(void);
+
+int mxs_reset_block(struct mxs_register_32 *reg);
+int mxs_wait_mask_set(struct mxs_register_32 *reg,
+ uint32_t mask,
+ unsigned int timeout);
+int mxs_wait_mask_clr(struct mxs_register_32 *reg,
+ uint32_t mask,
+ unsigned int timeout);
#endif