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authorTom Rini <trini@ti.com>2011-11-18 12:48:09 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2011-12-06 23:59:38 +0100
commit673283f3fc2583a56b3be995cd341159428734ba (patch)
tree31c3ec0d2ac75d8c82fe39504d71e6441c413652 /arch/arm
parent75c57a3570ec0904c14394db08ef436a8b49dda4 (diff)
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OMAP3: Add SPL support to omap3_evm
Add Hynix 200MHz timing information to <asm/arch-omap3/mem.h>. This also changes CONFIG_SYS_TEXT_BASE to 0x80100000. Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/include/asm/arch-omap3/mem.h26
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
index 4ea5f74..5fd02d4 100644
--- a/arch/arm/include/asm/arch-omap3/mem.h
+++ b/arch/arm/include/asm/arch-omap3/mem.h
@@ -123,6 +123,32 @@ enum {
V_MCFG_BANKALLOCATION_RBC | \
V_MCFG_B32NOT16_32 | V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR
+/* Hynix part of AM/DM37xEVM (200MHz optimized) */
+#define HYNIX_TDAL_200 6
+#define HYNIX_TDPL_200 3
+#define HYNIX_TRRD_200 2
+#define HYNIX_TRCD_200 4
+#define HYNIX_TRP_200 3
+#define HYNIX_TRAS_200 8
+#define HYNIX_TRC_200 11
+#define HYNIX_TRFC_200 18
+#define HYNIX_V_ACTIMA_200 \
+ ACTIM_CTRLA(HYNIX_TRFC_200, HYNIX_TRC_200, \
+ HYNIX_TRAS_200, HYNIX_TRP_200, \
+ HYNIX_TRCD_200, HYNIX_TRRD_200, \
+ HYNIX_TDPL_200, HYNIX_TDAL_200)
+
+#define HYNIX_TWTR_200 2
+#define HYNIX_TCKE_200 1
+#define HYNIX_TXP_200 1
+#define HYNIX_XSR_200 28
+#define HYNIX_V_ACTIMB_200 \
+ ACTIM_CTRLB(HYNIX_TWTR_200, HYNIX_TCKE_200, \
+ HYNIX_TXP_200, HYNIX_XSR_200)
+
+#define HYNIX_RASWIDTH_200 0x3
+#define HYNIX_V_MCFG_200(size) MCFG((size), HYNIX_RASWIDTH_200)
+
/* Infineon part of 3430SDP (165MHz optimized) 6.06ns */
#define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */
/* 15/6 + 18/6 = 5.5 -> 6 */