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| author | Nitin Garg <nitin.garg@freescale.com> | 2014-04-01 22:17:37 -0500 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2014-04-02 19:45:26 -0500 |
| commit | 56c705fc1bee6b8655d779e1f23d178eb742f532 (patch) | |
| tree | 95a774f1faf53c56fcca788b91c6e0dbf494756a /arch/arm | |
| parent | dad83b10276a3166c5e04af7cbcd7446df2fd651 (diff) | |
| download | u-boot-imx-56c705fc1bee6b8655d779e1f23d178eb742f532.zip u-boot-imx-56c705fc1bee6b8655d779e1f23d178eb742f532.tar.gz u-boot-imx-56c705fc1bee6b8655d779e1f23d178eb742f532.tar.bz2 | |
ENGR00306276-1: ARM: Add workaround for Cortex-A9 errata 794072
A short loop including a DMB instruction might cause a denial of
service on another processor which executes a CP15 broadcast operation.
Exists on r1, r2, r3, r4 revisions.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/armv7/start.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index e9e57e6..38b6021 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -315,7 +315,7 @@ ENTRY(cpu_init_cp15) mcr p15, 0, r0, c1, c0, 0 @ write system control register #endif -#ifdef CONFIG_ARM_ERRATA_742230 +#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072)) mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register orr r0, r0, #1 << 4 @ set bit #4 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register |