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| author | Jason Liu <r64343@freescale.com> | 2013-05-23 10:24:51 +0800 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2013-05-24 09:27:06 +0800 |
| commit | 6f04955aa81e688087ed6cf73802f8acfe065fe5 (patch) | |
| tree | a4d476ab7e517cffbe682afce4bc242d2e4667bc /arch/arm | |
| parent | ebceaad8a25d965485aec57ec7dd9dde4dcffe21 (diff) | |
| download | u-boot-imx-6f04955aa81e688087ed6cf73802f8acfe065fe5.zip u-boot-imx-6f04955aa81e688087ed6cf73802f8acfe065fe5.tar.gz u-boot-imx-6f04955aa81e688087ed6cf73802f8acfe065fe5.tar.bz2 | |
ENGR00264076-3 i.mx6:gate/ungate PFD before using it
Per the IC design, we need to gate/ungate all the unused PFDs
to make sure PFD is working correctly, otherwise, PFDs may not
not output clock after reset.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 05e165e..2e84d89 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -289,6 +289,42 @@ void check_cpu_temperature(void) printf("CPU: Temperature: can't get valid data!\n"); } +static void imx_reset_pfd(void) +{ + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + + /* + * Per the IC design, we need to gate/ungate all the unused PFDs + * to make sure PFD is working correctly, otherwise, PFDs may not + * not output clock after reset. + */ + + writel(BM_ANADIG_PFD_480_PFD3_CLKGATE | + BM_ANADIG_PFD_480_PFD2_CLKGATE | + BM_ANADIG_PFD_480_PFD1_CLKGATE | + BM_ANADIG_PFD_480_PFD0_CLKGATE, &anatop->pfd_480_set); +#ifdef CONFIG_MX6Q + writel(BM_ANADIG_PFD_528_PFD2_CLKGATE | + BM_ANADIG_PFD_528_PFD1_CLKGATE | + BM_ANADIG_PFD_528_PFD0_CLKGATE, &anatop->pfd_528_set); +#else + writel(BM_ANADIG_PFD_528_PFD1_CLKGATE | + BM_ANADIG_PFD_528_PFD0_CLKGATE, &anatop->pfd_528_set); +#endif + writel(BM_ANADIG_PFD_480_PFD3_CLKGATE | + BM_ANADIG_PFD_480_PFD2_CLKGATE | + BM_ANADIG_PFD_480_PFD1_CLKGATE | + BM_ANADIG_PFD_480_PFD0_CLKGATE, &anatop->pfd_480_clr); +#ifdef CONFIG_MX6Q + writel(BM_ANADIG_PFD_528_PFD2_CLKGATE | + BM_ANADIG_PFD_528_PFD1_CLKGATE | + BM_ANADIG_PFD_528_PFD0_CLKGATE, &anatop->pfd_528_clr); +#else + writel(BM_ANADIG_PFD_528_PFD1_CLKGATE | + BM_ANADIG_PFD_528_PFD0_CLKGATE, &anatop->pfd_528_clr); +#endif +} + int arch_cpu_init(void) { init_aips(); @@ -296,6 +332,8 @@ int arch_cpu_init(void) imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ + imx_reset_pfd(); + #ifdef CONFIG_APBH_DMA /* Start APBH DMA */ mxs_dma_init(); |