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| author | Tom Rini <trini@ti.com> | 2011-11-18 12:47:58 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-12-06 23:59:37 +0100 |
| commit | b7eb9e7895bf481d979d58d5d7a53033c3ad9a8f (patch) | |
| tree | 2521afc99574337a9c8d40e15cfeca0bc3aed98a /arch/arm | |
| parent | b609009801b8a00644926f49b7d0d0cc0d3d8797 (diff) | |
| download | u-boot-imx-b7eb9e7895bf481d979d58d5d7a53033c3ad9a8f.zip u-boot-imx-b7eb9e7895bf481d979d58d5d7a53033c3ad9a8f.tar.gz u-boot-imx-b7eb9e7895bf481d979d58d5d7a53033c3ad9a8f.tar.bz2 | |
omap3: mem: Comment enable_gpmc_cs_config more
Expand the "enable the config" comment to explain what the bit shifts
are and define out two of the magic numbers.
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/armv7/omap3/mem.c | 12 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-omap3/mem.h | 4 |
2 files changed, 13 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv7/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c index a01c303..2f1efea 100644 --- a/arch/arm/cpu/armv7/omap3/mem.c +++ b/arch/arm/cpu/armv7/omap3/mem.c @@ -105,9 +105,15 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, writel(gpmc_config[3], &cs->config4); writel(gpmc_config[4], &cs->config5); writel(gpmc_config[5], &cs->config6); - /* Enable the config */ - writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | - (1 << 6)), &cs->config7); + + /* + * Enable the config. size is the CS size and goes in + * bits 11:8. We set bit 6 to enable this CS and the base + * address goes into bits 5:0. + */ + writel((size << 8) | (GPMC_CS_ENABLE << 6) | + ((base >> 24) & GPMC_BASEADDR_MASK), + &cs->config7); sdelay(2000); } diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index db6a696..abf4e82 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -259,6 +259,10 @@ enum { #define GPMC_SIZE_32M 0xE #define GPMC_SIZE_16M 0xF +#define GPMC_BASEADDR_MASK 0x3F + +#define GPMC_CS_ENABLE 0x1 + #define SMNAND_GPMC_CONFIG1 0x00000800 #define SMNAND_GPMC_CONFIG2 0x00141400 #define SMNAND_GPMC_CONFIG3 0x00141400 |