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author | Stefan Roese <sr@denx.de> | 2015-01-19 11:33:42 +0100 |
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committer | Luka Perkov <luka.perkov@sartura.hr> | 2015-02-06 17:24:56 +0100 |
commit | b0f80b913f5a8aec8ba75093328ac17d178c3b95 (patch) | |
tree | 8ff1efd290cf4720365af982990358d86ca41555 /arch/arm/mvebu-common | |
parent | 0cf47862bf647690762c841e247fb5b097ca7316 (diff) | |
download | u-boot-imx-b0f80b913f5a8aec8ba75093328ac17d178c3b95.zip u-boot-imx-b0f80b913f5a8aec8ba75093328ac17d178c3b95.tar.gz u-boot-imx-b0f80b913f5a8aec8ba75093328ac17d178c3b95.tar.bz2 |
arm: armada-xp: Add SPL support used to include the DDR training code
This patch adds SPL support to the Marvell Armada-XP. With this addition
the bin_hdr integration is not needed any more. The SPL will first
initialize the serdes/PHY and the call the DDR setup and training code
now integrated into mainline U-Boot.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
Diffstat (limited to 'arch/arm/mvebu-common')
-rw-r--r-- | arch/arm/mvebu-common/u-boot-spl.lds | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/arch/arm/mvebu-common/u-boot-spl.lds b/arch/arm/mvebu-common/u-boot-spl.lds new file mode 100644 index 0000000..eee1db4 --- /dev/null +++ b/arch/arm/mvebu-common/u-boot-spl.lds @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * Aneesh V <aneesh@ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : + { + __start = .; + arch/arm/cpu/armv7/start.o (.text*) + *(.text*) + *(.vectors) + } >.sram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*_i2c_*))); + } >.sram + + . = ALIGN(4); + __image_copy_end = .; + + .end : + { + *(.__end) + } + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } >.sdram +} |