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author | Tom Rini <trini@konsulko.com> | 2016-04-13 12:53:11 -0400 |
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committer | Tom Rini <trini@konsulko.com> | 2016-04-13 12:53:11 -0400 |
commit | 541c9be880d601cb0230dc7452c398167ed1eaac (patch) | |
tree | 0686261e2d2e4589c651d165026d4e678390915a /arch/arm/mach-zynq/include/mach/gpio.h | |
parent | 3f8085e94ae3e8a2996e2f517ecdb608a4b4c09e (diff) | |
parent | 58ed7f66939cbfb6e48656b3925aefd9f180a1a3 (diff) | |
download | u-boot-imx-541c9be880d601cb0230dc7452c398167ed1eaac.zip u-boot-imx-541c9be880d601cb0230dc7452c398167ed1eaac.tar.gz u-boot-imx-541c9be880d601cb0230dc7452c398167ed1eaac.tar.bz2 |
Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze
Diffstat (limited to 'arch/arm/mach-zynq/include/mach/gpio.h')
-rw-r--r-- | arch/arm/mach-zynq/include/mach/gpio.h | 63 |
1 files changed, 0 insertions, 63 deletions
diff --git a/arch/arm/mach-zynq/include/mach/gpio.h b/arch/arm/mach-zynq/include/mach/gpio.h index 0789c49..f3dfd65 100644 --- a/arch/arm/mach-zynq/include/mach/gpio.h +++ b/arch/arm/mach-zynq/include/mach/gpio.h @@ -8,67 +8,4 @@ #ifndef _ZYNQ_GPIO_H #define _ZYNQ_GPIO_H -#define ZYNQ_GPIO_BASE_ADDRESS 0xE000A000 - -/* Maximum banks */ -#define ZYNQ_GPIO_MAX_BANK 4 - -#define ZYNQ_GPIO_BANK0_NGPIO 32 -#define ZYNQ_GPIO_BANK1_NGPIO 22 -#define ZYNQ_GPIO_BANK2_NGPIO 32 -#define ZYNQ_GPIO_BANK3_NGPIO 32 - -#define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \ - ZYNQ_GPIO_BANK1_NGPIO + \ - ZYNQ_GPIO_BANK2_NGPIO + \ - ZYNQ_GPIO_BANK3_NGPIO) - -#define ZYNQ_GPIO_BANK0_PIN_MIN 0 -#define ZYNQ_GPIO_BANK0_PIN_MAX (ZYNQ_GPIO_BANK0_PIN_MIN + \ - ZYNQ_GPIO_BANK0_NGPIO - 1) -#define ZYNQ_GPIO_BANK1_PIN_MIN (ZYNQ_GPIO_BANK0_PIN_MAX + 1) -#define ZYNQ_GPIO_BANK1_PIN_MAX (ZYNQ_GPIO_BANK1_PIN_MIN + \ - ZYNQ_GPIO_BANK1_NGPIO - 1) -#define ZYNQ_GPIO_BANK2_PIN_MIN (ZYNQ_GPIO_BANK1_PIN_MAX + 1) -#define ZYNQ_GPIO_BANK2_PIN_MAX (ZYNQ_GPIO_BANK2_PIN_MIN + \ - ZYNQ_GPIO_BANK2_NGPIO - 1) -#define ZYNQ_GPIO_BANK3_PIN_MIN (ZYNQ_GPIO_BANK2_PIN_MAX + 1) -#define ZYNQ_GPIO_BANK3_PIN_MAX (ZYNQ_GPIO_BANK3_PIN_MIN + \ - ZYNQ_GPIO_BANK3_NGPIO - 1) - -/* Register offsets for the GPIO device */ -/* LSW Mask & Data -WO */ -#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK)) -/* MSW Mask & Data -WO */ -#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK)) -/* Data Register-RW */ -#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK)) -/* Direction mode reg-RW */ -#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK)) -/* Output enable reg-RW */ -#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK)) -/* Interrupt mask reg-RO */ -#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK)) -/* Interrupt enable reg-WO */ -#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK)) -/* Interrupt disable reg-WO */ -#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK)) -/* Interrupt status reg-RO */ -#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK)) -/* Interrupt type reg-RW */ -#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK)) -/* Interrupt polarity reg-RW */ -#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK)) -/* Interrupt on any, reg-RW */ -#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK)) - -/* Disable all interrupts mask */ -#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF - -/* Mid pin number of a bank */ -#define ZYNQ_GPIO_MID_PIN_NUM 16 - -/* GPIO upper 16 bit mask */ -#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000 - #endif /* _ZYNQ_GPIO_H */ |