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author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2015-03-16 16:43:23 +0900 |
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committer | Michal Simek <michal.simek@xilinx.com> | 2015-04-29 11:19:05 +0200 |
commit | 9b9c6516b0119a4abe71b1598b2258c591f955f5 (patch) | |
tree | ee43008b510e80939bd79974e3330ff32b682dff /arch/arm/mach-zynq/include/mach/clk.h | |
parent | 0107f2403669f764ab726d0d404e35bb9447bbcc (diff) | |
download | u-boot-imx-9b9c6516b0119a4abe71b1598b2258c591f955f5.zip u-boot-imx-9b9c6516b0119a4abe71b1598b2258c591f955f5.tar.gz u-boot-imx-9b9c6516b0119a4abe71b1598b2258c591f955f5.tar.bz2 |
ARM: zynq: move SoC headers to mach-zynq/include/mach
Move arch/arm/include/asm/arch-zynq/*
-> arch/arm/mach-zynq/include/mach/*
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/mach-zynq/include/mach/clk.h')
-rw-r--r-- | arch/arm/mach-zynq/include/mach/clk.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm/mach-zynq/include/mach/clk.h b/arch/arm/mach-zynq/include/mach/clk.h new file mode 100644 index 0000000..250c5bc --- /dev/null +++ b/arch/arm/mach-zynq/include/mach/clk.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2013 Xilinx Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ZYNQ_CLK_H_ +#define _ZYNQ_CLK_H_ + +enum zynq_clk { + armpll_clk, ddrpll_clk, iopll_clk, + cpu_6or4x_clk, cpu_3or2x_clk, cpu_2x_clk, cpu_1x_clk, + ddr2x_clk, ddr3x_clk, dci_clk, + lqspi_clk, smc_clk, pcap_clk, gem0_clk, gem1_clk, + fclk0_clk, fclk1_clk, fclk2_clk, fclk3_clk, can0_clk, can1_clk, + sdio0_clk, sdio1_clk, uart0_clk, uart1_clk, spi0_clk, spi1_clk, dma_clk, + usb0_aper_clk, usb1_aper_clk, gem0_aper_clk, gem1_aper_clk, + sdio0_aper_clk, sdio1_aper_clk, spi0_aper_clk, spi1_aper_clk, + can0_aper_clk, can1_aper_clk, i2c0_aper_clk, i2c1_aper_clk, + uart0_aper_clk, uart1_aper_clk, gpio_aper_clk, lqspi_aper_clk, + smc_aper_clk, swdt_clk, dbg_trc_clk, dbg_apb_clk, clk_max}; + +void zynq_clk_early_init(void); +int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate); +unsigned long zynq_clk_get_rate(enum zynq_clk clk); +const char *zynq_clk_get_name(enum zynq_clk clk); +unsigned long get_uart_clk(int dev_id); + +#endif |