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author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-03-18 16:41:44 +0900 |
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committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-03-24 01:45:18 +0900 |
commit | 5d0607c58c02204c7ec02f0f4d6bd268929961ee (patch) | |
tree | 24aecfd06a5712f8438a3b5f68ad354372156689 /arch/arm/mach-uniphier/sbc/sbc-admulti.c | |
parent | ea65c98050f0f13f933119e1d073c8a138481ee4 (diff) | |
download | u-boot-imx-5d0607c58c02204c7ec02f0f4d6bd268929961ee.zip u-boot-imx-5d0607c58c02204c7ec02f0f4d6bd268929961ee.tar.gz u-boot-imx-5d0607c58c02204c7ec02f0f4d6bd268929961ee.tar.bz2 |
ARM: uniphier: refactor SBC init code
There is a bunch of duplication in the System Bus Controller init
code. Roughly, there are two types in the SBC mode: Adress/Data
Multiplex Mode and Save Pins Mode. Consolidate per-SoC functions
into the two, plus per-SoC optional init code.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/sbc/sbc-admulti.c')
-rw-r--r-- | arch/arm/mach-uniphier/sbc/sbc-admulti.c | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/arch/arm/mach-uniphier/sbc/sbc-admulti.c b/arch/arm/mach-uniphier/sbc/sbc-admulti.c new file mode 100644 index 0000000..8e9f8eb --- /dev/null +++ b/arch/arm/mach-uniphier/sbc/sbc-admulti.c @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/io.h> + +#include "../init.h" +#include "../sg-regs.h" +#include "sbc-regs.h" + +#define SBCTRL0_ADMULTIPLX_PERI_VALUE 0x33120000 +#define SBCTRL1_ADMULTIPLX_PERI_VALUE 0x03005500 +#define SBCTRL2_ADMULTIPLX_PERI_VALUE 0x14000020 + +#define SBCTRL0_ADMULTIPLX_MEM_VALUE 0x33120000 +#define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500 +#define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010 + +int sbc_admulti_init(const struct uniphier_board_data *bd) +{ + /* + * Only CS1 is connected to support card. + * BKSZ[1:0] should be set to "01". + */ + writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10); + writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11); + writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12); + + if (boot_is_swapped()) { + /* + * Boot Swap On: boot from external NOR/SRAM + * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff. + * + * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank + * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals + */ + writel(0x0000bc01, SBBASE0); + } else { + /* + * Boot Swap Off: boot from mask ROM + * 0x40000000-0x41ffffff: mask ROM + * 0x42000000-0x43efffff: memory bank (31MB) + * 0x43f00000-0x43ffffff: peripherals (1MB) + */ + writel(0x0000be01, SBBASE0); /* dummy */ + writel(0x0200be01, SBBASE1); + } + + return 0; +} |