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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-09-17 03:33:04 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-09-18 23:10:44 +0900 |
| commit | 5ac9dfbe9d9a19b04ddb306e7d6833861f9b6f72 (patch) | |
| tree | 4b3b0dbb2acf69140460079ff2b0c908c90d9cd2 /arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c | |
| parent | 6a93478b93390a123b1d85512d66c093843e3f9b (diff) | |
| download | u-boot-imx-5ac9dfbe9d9a19b04ddb306e7d6833861f9b6f72.zip u-boot-imx-5ac9dfbe9d9a19b04ddb306e7d6833861f9b6f72.tar.gz u-boot-imx-5ac9dfbe9d9a19b04ddb306e7d6833861f9b6f72.tar.bz2 | |
ARM: uniphier: consolidate NAND pin-mux settings
The NAND subsystem has not supported the Driver Model yet, but the
NAND pin-mux data are already in the pinctrl drivers. Use them by
calling pinctrl_generic_set_state() directly.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c')
| -rw-r--r-- | arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c | 19 |
1 files changed, 0 insertions, 19 deletions
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c index ec4c414..e1cb90a 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c @@ -13,25 +13,6 @@ void uniphier_ld20_pin_init(void) { /* Comment format: PAD Name -> Function Name */ -#ifdef CONFIG_NAND_DENALI - sg_set_pinsel(3, 0, 8, 4); /* XNFWP -> XNFWP */ - sg_set_pinsel(4, 0, 8, 4); /* XNFCE0 -> XNFCE0 */ - sg_set_pinsel(5, 0, 8, 4); /* NFRYBY0 -> NFRYBY0 */ - sg_set_pinsel(6, 0, 8, 4); /* XNFRE -> XNFRE */ - sg_set_pinsel(7, 0, 8, 4); /* XNFWE -> XNFWE */ - sg_set_pinsel(8, 0, 8, 4); /* NFALE -> NFALE */ - sg_set_pinsel(9, 0, 8, 4); /* NFCLE -> NFCLE */ - sg_set_pinsel(10, 0, 8, 4); /* NFD0 -> NFD0 */ - sg_set_pinsel(11, 0, 8, 4); /* NFD1 -> NFD1 */ - sg_set_pinsel(12, 0, 8, 4); /* NFD2 -> NFD2 */ - sg_set_pinsel(13, 0, 8, 4); /* NFD3 -> NFD3 */ - sg_set_pinsel(14, 0, 8, 4); /* NFD4 -> NFD4 */ - sg_set_pinsel(15, 0, 8, 4); /* NFD5 -> NFD5 */ - sg_set_pinsel(16, 0, 8, 4); /* NFD6 -> NFD6 */ - sg_set_pinsel(17, 0, 8, 4); /* NFD7 -> NFD7 */ - sg_set_iectrl_range(3, 17); -#endif - sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */ sg_set_iectrl(149); sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */ |