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author | Masahiro Yamada <yamada.m@jp.panasonic.com> | 2015-02-27 02:26:49 +0900 |
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committer | Masahiro Yamada <yamada.m@jp.panasonic.com> | 2015-03-01 00:02:29 +0900 |
commit | 27eac5df175be016a391cedf37cf5a076d279cf8 (patch) | |
tree | 573d9d6a0e1da43f716323440261b2786d1f72ec /arch/arm/mach-uniphier/ph1-pro4 | |
parent | 1a745d27bde339b2491246d69aee9b9a3f39c692 (diff) | |
download | u-boot-imx-27eac5df175be016a391cedf37cf5a076d279cf8.zip u-boot-imx-27eac5df175be016a391cedf37cf5a076d279cf8.tar.gz u-boot-imx-27eac5df175be016a391cedf37cf5a076d279cf8.tar.bz2 |
ARM: UniPhier: fix SBC init code
Now UniPhier SoCs only work with CONFIG_SPL and the function
sbc_init() is called from SPL.
The conditional #if !defined(CONFIG_SPL_BUILD) has no point
any more.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Diffstat (limited to 'arch/arm/mach-uniphier/ph1-pro4')
-rw-r--r-- | arch/arm/mach-uniphier/ph1-pro4/sbc_init.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c b/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c index 6940559..4cc5e75 100644 --- a/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c +++ b/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c @@ -42,13 +42,12 @@ void sbc_init(void) writel(0x0200be01, SBBASE1); } #elif defined(CONFIG_DCC_MICRO_SUPPORT_CARD) -#if !defined(CONFIG_SPL_BUILD) /* XECS0: boot/sub memory (boot swap = off/on) */ writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00); writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01); writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02); writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04); -#endif + /* XECS1: sub/boot memory (boot swap = off/on) */ writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); @@ -65,9 +64,10 @@ void sbc_init(void) writel(0x0400bc01, SBBASE1); /* sub memory */ writel(0x0800bf01, SBBASE3); /* peripherals */ -#if !defined(CONFIG_SPL_BUILD) - sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */ -#endif + /* enable access to sub memory when boot swap is on */ + if (boot_is_swapped()) + sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */ + sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */ writel(0x00000001, SG_LOADPINCTRL); |