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| author | Masahiro Yamada <yamada.m@jp.panasonic.com> | 2015-02-27 02:26:42 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.m@jp.panasonic.com> | 2015-03-01 00:01:56 +0900 |
| commit | 4c425570214cac091d9bdcf840b936062fb8da12 (patch) | |
| tree | a8a83c219c46dec073438df0c77031418c662b25 /arch/arm/mach-uniphier/ph1-ld4/sbc_init.c | |
| parent | 1606b34aa50804227806971dbb6b82ea0bf81f55 (diff) | |
| download | u-boot-imx-4c425570214cac091d9bdcf840b936062fb8da12.zip u-boot-imx-4c425570214cac091d9bdcf840b936062fb8da12.tar.gz u-boot-imx-4c425570214cac091d9bdcf840b936062fb8da12.tar.bz2 | |
ARM: UniPhier: move SoC sources to mach-uniphier
Move
arch/arm/cpu/armv7/uniphier/* -> arch/arm/mach-uniphier/*
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Diffstat (limited to 'arch/arm/mach-uniphier/ph1-ld4/sbc_init.c')
| -rw-r--r-- | arch/arm/mach-uniphier/ph1-ld4/sbc_init.c | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c b/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c new file mode 100644 index 0000000..4839c94 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sbc-regs.h> +#include <asm/arch/sg-regs.h> + +void sbc_init(void) +{ + u32 tmp; + + /* system bus output enable */ + tmp = readl(PC0CTRL); + tmp &= 0xfffffcff; + writel(tmp, PC0CTRL); + + /* XECS1: sub/boot memory (boot swap = off/on) */ + writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); + writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); + writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); + writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); + +#if !defined(CONFIG_SPL_BUILD) + /* XECS0: boot/sub memory (boot swap = off/on) */ + writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00); + writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01); + writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02); + writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04); +#endif + /* XECS3: peripherals */ + writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30); + writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31); + writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32); + writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34); + + /* base address regsiters */ + writel(0x0000bc01, SBBASE0); + writel(0x0400bc01, SBBASE1); + writel(0x0800bf01, SBBASE3); + +#if !defined(CONFIG_SPL_BUILD) + /* enable access to sub memory when boot swap is on */ + sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */ +#endif + sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */ +} |