ARM: uniphier: allow to enable multiple SoCs

Before this commit, the Kconfig menu in mach-uniphier only allowed us
to choose one SoC to be compiled.  Each SoC has its own defconfig file
for the build-test coverage.  Consequently, some defconfig files are
duplicated with only the difference in CONFIG_DEFAULT_DEVICE_TREE and
CONFIG_{SOC_NAME}=y.

Now, most of board-specific parameters have been moved to device trees,
so it makes sense to include init code of multiple SoCs into a single
image as long as the SoCs have similar architecture.  In fact, some
SoCs of UniPhier family are very similar:
 - PH1-LD4 and PH1-sLD8
 - PH1-LD6b and ProXstream2 (will be added in the upcoming commit)

This commit will be helpful to merge some defconfig files for better
maintainability.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

1 files changed, 0 insertions, 49 deletions

diff --git a/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c b/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c
deleted file mode 100644
index 4435a47..0000000
--- a/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
-
-void sbc_init(void)
-{
-	u32 tmp;
-
-	/* system bus output enable */
-	tmp = readl(PC0CTRL);
-	tmp &= 0xfffffcff;
-	writel(tmp, PC0CTRL);
-
-	/*
-	 * Only CS1 is connected to support card.
-	 * BKSZ[1:0] should be set to "01".
-	 */
-	writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
-	writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
-	writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
-	writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
-
-	if (boot_is_swapped()) {
-		/*
-		 * Boot Swap On: boot from external NOR/SRAM
-		 * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
-		 *
-		 * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
-		 * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
-		 */
-		writel(0x0000bc01, SBBASE0);
-	} else {
-		/*
-		 * Boot Swap Off: boot from mask ROM
-		 * 0x40000000-0x41ffffff: mask ROM
-		 * 0x42000000-0x43efffff: memory bank (31MB)
-		 * 0x43f00000-0x43ffffff: peripherals (1MB)
-		 */
-		writel(0x0000be01, SBBASE0); /* dummy */
-		writel(0x0200be01, SBBASE1);
-	}
-}