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authorMasahiro Yamada <yamada.masahiro@socionext.com>2015-03-23 00:07:30 +0900
committerMasahiro Yamada <yamada.masahiro@socionext.com>2015-03-24 00:15:52 +0900
commit4d13b1b708b8c31c0e22d7f31f05dde4b3961621 (patch)
tree7da83136a8380e84c7213b07c43b533178d0246d /arch/arm/mach-uniphier/lowlevel_init.S
parentdef3feb8cbfd44f2cfec73db4cf54760eaa97ed6 (diff)
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ARM: UniPhier: fix typos in comments
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/lowlevel_init.S')
-rw-r--r--arch/arm/mach-uniphier/lowlevel_init.S14
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/mach-uniphier/lowlevel_init.S b/arch/arm/mach-uniphier/lowlevel_init.S
index 3a3ada8..4a23ea4 100644
--- a/arch/arm/mach-uniphier/lowlevel_init.S
+++ b/arch/arm/mach-uniphier/lowlevel_init.S
@@ -25,8 +25,8 @@ ENTRY(lowlevel_init)
* First we need to turn on MMU and Dcache again to get back
* data access to L2.
*/
- mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
- orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache
+ mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
+ orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache
mcr p15, 0, r0, c1, c0, 0
#ifdef CONFIG_DEBUG_LL
@@ -41,7 +41,7 @@ ENTRY(lowlevel_init)
ldr r3, =init_page_table @ page table must be 16KB aligned
/* Disable MMU and Dcache before switching Page Table */
- mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
+ mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache
mcr p15, 0, r0, c1, c0, 0
@@ -55,7 +55,7 @@ ENTRY(lowlevel_init)
* bit[7] EXCL (Exclusive cache bit)
* bit[6] SMP
* bit[3] Write full line of zeros mode
- * bit[2] L1 Prefetch enable
+ * bit[2] L1 prefetch enable
* bit[1] L2 prefetch enable
* bit[0] FW (Cache and TLB maintenance broadcast)
*/
@@ -81,7 +81,7 @@ primary_cpu:
ldr r0, =_start @ entry for the secondary CPU
str r0, [r1]
ldr r0, [r1] @ make sure str is complete before sev
- sev @ kick the sedoncary CPU
+ sev @ kick the secondary CPU
mrc p15, 4, r1, c15, c0, 0 @ Configuration Base Address Register
bfc r1, #0, #13 @ clear bit 12-0
mov r0, #-1
@@ -118,7 +118,7 @@ ENTRY(enable_mmu)
* TLBs was already invalidated in "../start.S"
* So, we don't need to invalidate it here.
*/
- mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
+ mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable
mcr p15, 0, r0, c1, c0, 0
@@ -155,7 +155,7 @@ ENTRY(setup_init_ram)
ldr r1, = SSCOPPQSEF
ldr r0, [r1]
cmp r0, #0 @ check if the command is successfully set
- bne 0b @ try again if an error occurres
+ bne 0b @ try again if an error occurs
ldr r1, = SSCOLPQS
1: