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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-02-26 14:21:42 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-02-29 03:50:16 +0900 |
| commit | 78876704984f44e96578f887035aabaec2b776f5 (patch) | |
| tree | 76499cb964a623e4b9668859a82925ed83d5f8ba /arch/arm/mach-uniphier/dram/umc-ph1-pro4.c | |
| parent | 4f19f6118478c8bbf4bd435404094b23991ad225 (diff) | |
| download | u-boot-imx-78876704984f44e96578f887035aabaec2b776f5.zip u-boot-imx-78876704984f44e96578f887035aabaec2b776f5.tar.gz u-boot-imx-78876704984f44e96578f887035aabaec2b776f5.tar.bz2 | |
ARM: uniphier: remove unused argument of ph1_ld4_ddrphy_init()
The DDR PHY settings no longer depend on the DRAM size. Drop the
argument from the init function.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/dram/umc-ph1-pro4.c')
| -rw-r--r-- | arch/arm/mach-uniphier/dram/umc-ph1-pro4.c | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c index 877f5ef..0a2485e 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c @@ -138,32 +138,28 @@ int ph1_pro4_umc_init(const struct uniphier_board_data *bd) writel(0x00000101, dramcont0 + UMC_DIOCTLA); - ph1_ld4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch[0].size, - bd->dram_ddr3plus); + ph1_ld4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ddr3plus); ddrphy_prepare_training(phy0_0, 0); ddrphy_training(phy0_0); writel(0x00000103, dramcont0 + UMC_DIOCTLA); - ph1_ld4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch[0].size, - bd->dram_ddr3plus); + ph1_ld4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ddr3plus); ddrphy_prepare_training(phy0_1, 1); ddrphy_training(phy0_1); writel(0x00000101, dramcont1 + UMC_DIOCTLA); - ph1_ld4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch[1].size, - bd->dram_ddr3plus); + ph1_ld4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ddr3plus); ddrphy_prepare_training(phy1_0, 0); ddrphy_training(phy1_0); writel(0x00000103, dramcont1 + UMC_DIOCTLA); - ph1_ld4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch[1].size, - bd->dram_ddr3plus); + ph1_ld4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ddr3plus); ddrphy_prepare_training(phy1_1, 1); ddrphy_training(phy1_1); |