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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-02-26 14:21:34 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-02-29 03:50:16 +0900 |
| commit | 46abfcc99e04efa75ed293bd871092c31d0f3be3 (patch) | |
| tree | e8574e16ce94aadb203124a6c8a52a105a64c194 /arch/arm/mach-uniphier/bcu | |
| parent | 8353266825d7b7d673519bce3a54cdddf2c3d459 (diff) | |
| download | u-boot-imx-46abfcc99e04efa75ed293bd871092c31d0f3be3.zip u-boot-imx-46abfcc99e04efa75ed293bd871092c31d0f3be3.tar.gz u-boot-imx-46abfcc99e04efa75ed293bd871092c31d0f3be3.tar.bz2 | |
ARM: uniphier: rework struct uniphier_board_data
This commit reworks "struct uniphier_board_data" with an array of
DRAM channel data in it. It will allow further cleanups by means of
"for" statements that iterate over the DDR channels.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/bcu')
| -rw-r--r-- | arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c b/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c index f82c7d1..bbe8a74 100644 --- a/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c +++ b/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c @@ -22,7 +22,7 @@ int ph1_ld4_bcu_init(const struct uniphier_board_data *bd) writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */ /* Specify DDR channel */ - shift = (bd->dram_ch1_base - bd->dram_ch0_base) / 0x04000000 * 4; + shift = (bd->dram_ch[1].base - bd->dram_ch[0].base) / 0x04000000 * 4; writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ shift -= 32; diff --git a/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c b/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c index 75ccd15..b7497e9 100644 --- a/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c +++ b/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c @@ -26,7 +26,7 @@ int ph1_sld3_bcu_init(const struct uniphier_board_data *bd) writel(0x24440000, BCSCR5); /* Specify DDR channel */ - shift = (bd->dram_ch1_base - bd->dram_ch0_base) / 0x04000000 * 4; + shift = (bd->dram_ch[1].base - bd->dram_ch[0].base) / 0x04000000 * 4; writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ shift -= 32; |