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authorStephen Warren <swarren@nvidia.com>2015-03-25 12:04:37 -0600
committerTom Warren <twarren@nvidia.com>2015-03-30 09:54:06 -0700
commit89d9437356ce9121f99889c11b55ed28fb8851b2 (patch)
treed47832c3e58c907a8cd09116643b02dab27dfcf8 /arch/arm/mach-tegra
parent5ee7ec7bafe6d02ebacdde06bb536f55cff4cdd8 (diff)
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ARM: tegra: enable MIPI PAD CTRL support for Tegra124
This allows selection between CSI and DSI_B on the MIPI pads. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra')
-rw-r--r--arch/arm/mach-tegra/tegra124/pinmux.c17
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra124/pinmux.c b/arch/arm/mach-tegra/tegra124/pinmux.c
index c6685ea..4629b46 100644
--- a/arch/arm/mach-tegra/tegra124/pinmux.c
+++ b/arch/arm/mach-tegra/tegra124/pinmux.c
@@ -304,3 +304,20 @@ static const struct pmux_pingrp_desc tegra124_pingroups[] = {
PIN(DP_HPD_PFF0, DP, RSVD2, RSVD3, RSVD4),
};
const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra124_pingroups;
+
+#define MIPIPADCTRL_GRP(grp, f0, f1) \
+ { \
+ .funcs = { \
+ PMUX_FUNC_##f0, \
+ PMUX_FUNC_##f1, \
+ }, \
+ }
+
+#define MIPIPADCTRL_RESERVED {}
+
+static const struct pmux_mipipadctrlgrp_desc tegra124_mipipadctrl_groups[] = {
+ /* pin, f0, f1 */
+ /* Offset 0x820 */
+ MIPIPADCTRL_GRP(DSI_B, CSI, DSI_B),
+};
+const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups = tegra124_mipipadctrl_groups;