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| author | Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | 2016-04-01 03:51:34 +0900 |
|---|---|---|
| committer | Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | 2016-08-17 10:25:35 +0900 |
| commit | 581183def6ec7e7695110ee75ea866b734c5e249 (patch) | |
| tree | 0ed23b3ed4fe11239091ee627175c55750dba891 /arch/arm/mach-rmobile/lowlevel_init_gen3.S | |
| parent | a7da6f8c3d6d685af9426cdc2357d2e66cff2875 (diff) | |
| download | u-boot-imx-581183def6ec7e7695110ee75ea866b734c5e249.zip u-boot-imx-581183def6ec7e7695110ee75ea866b734c5e249.tar.gz u-boot-imx-581183def6ec7e7695110ee75ea866b734c5e249.tar.bz2 | |
ARM: rmobile: Add support R-Car Generation 3
This adds supporting R-Car Generation 3 (Gen3) as Renesas ARM64 SoC.
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'arch/arm/mach-rmobile/lowlevel_init_gen3.S')
| -rw-r--r-- | arch/arm/mach-rmobile/lowlevel_init_gen3.S | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/arch/arm/mach-rmobile/lowlevel_init_gen3.S b/arch/arm/mach-rmobile/lowlevel_init_gen3.S new file mode 100644 index 0000000..88ff56e --- /dev/null +++ b/arch/arm/mach-rmobile/lowlevel_init_gen3.S @@ -0,0 +1,76 @@ +/* + * arch/arm/cpu/armv8/rcar_gen3/lowlevel_init.S + * This file is lowlevel initialize routine. + * + * (C) Copyright 2015 Renesas Electronics Corporation + * + * This file is based on the arch/arm/cpu/armv8/start.S + * + * (C) Copyright 2013 + * David Feng <fenghua@phytium.com.cn> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm-offsets.h> +#include <config.h> +#include <linux/linkage.h> +#include <asm/macro.h> + +ENTRY(lowlevel_init) + mov x29, lr /* Save LR */ + +#ifndef CONFIG_ARMV8_MULTIENTRY + /* + * For single-entry systems the lowlevel init is very simple. + */ + ldr x0, =GICD_BASE + bl gic_init_secure + +#else /* CONFIG_ARMV8_MULTIENTRY is set */ + +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) + branch_if_slave x0, 1f + ldr x0, =GICD_BASE + bl gic_init_secure +1: +#if defined(CONFIG_GICV3) + ldr x0, =GICR_BASE + bl gic_init_secure_percpu +#elif defined(CONFIG_GICV2) + ldr x0, =GICD_BASE + ldr x1, =GICC_BASE + bl gic_init_secure_percpu +#endif +#endif + + branch_if_master x0, x1, 2f + + /* + * Slave should wait for master clearing spin table. + * This sync prevent salves observing incorrect + * value of spin table and jumping to wrong place. + */ +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) +#ifdef CONFIG_GICV2 + ldr x0, =GICC_BASE +#endif + bl gic_wait_for_interrupt +#endif + + /* + * All slaves will enter EL2 and optionally EL1. + */ + bl armv8_switch_to_el2 +#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 + bl armv8_switch_to_el1 +#endif + +#endif /* CONFIG_ARMV8_MULTIENTRY */ + + bl s_init + +2: + mov lr, x29 /* Restore LR */ + ret +ENDPROC(lowlevel_init) |