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authorMasahiro Yamada <yamada.m@jp.panasonic.com>2015-02-20 17:04:06 +0900
committerTom Rini <trini@ti.com>2015-02-21 08:23:51 -0500
commit56f86e39e80c5cbb17bec42cf6931cd203176830 (patch)
treeffbea779443e952e83c1515b51238bca64353a35 /arch/arm/mach-kirkwood
parent601fbec7cf815bc2b26ba2546ac5e8501fc7edae (diff)
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ARM: kirkwood: move SOC sources to mach-kirkwood
Move arch/arm/cpu/arm926ejs/kirkwood/* -> arch/arm/mach-kirkwood/* Note: Perhaps, can we merge arch/arm/mach-kirkwood and arch/arm/mvebu-common into arch/arm/mach-mvebu, like Linux? Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Stefan Roese <sr@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
Diffstat (limited to 'arch/arm/mach-kirkwood')
-rw-r--r--arch/arm/mach-kirkwood/Kconfig88
-rw-r--r--arch/arm/mach-kirkwood/Makefile11
-rw-r--r--arch/arm/mach-kirkwood/cache.c19
-rw-r--r--arch/arm/mach-kirkwood/cpu.c321
-rw-r--r--arch/arm/mach-kirkwood/mpp.c90
5 files changed, 529 insertions, 0 deletions
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
new file mode 100644
index 0000000..45c6687
--- /dev/null
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -0,0 +1,88 @@
+if KIRKWOOD
+
+choice
+ prompt "Marvell Kirkwood board select"
+
+config TARGET_OPENRD
+ bool "Marvell OpenRD Board"
+
+config TARGET_MV88F6281GTW_GE
+ bool "MV88f6281GTW_GE Board"
+
+config TARGET_RD6281A
+ bool "RD6281A Board"
+
+config TARGET_DREAMPLUG
+ bool "DreamPlug Board"
+
+config TARGET_GURUPLUG
+ bool "GuruPlug Board"
+
+config TARGET_SHEEVAPLUG
+ bool "SheevaPlug Board"
+
+config TARGET_LSXL
+ bool "lsxl Board"
+
+config TARGET_POGO_E02
+ bool "pogo_e02 Board"
+
+config TARGET_DNS325
+ bool "dns325 Board"
+
+config TARGET_ICONNECT
+ bool "iconnect Board"
+
+config TARGET_TK71
+ bool "TK71 Board"
+
+config TARGET_KM_KIRKWOOD
+ bool "KM_KIRKWOOD Board"
+
+config TARGET_NET2BIG_V2
+ bool "LaCie 2Big Network v2 NAS Board"
+
+config TARGET_NETSPACE_V2
+ bool "LaCie netspace_v2 Board"
+
+config TARGET_WIRELESS_SPACE
+ bool "LaCie Wireless_space Board"
+
+config TARGET_IB62X0
+ bool "ib62x0 Board"
+
+config TARGET_DOCKSTAR
+ bool "Dockstar Board"
+
+config TARGET_GOFLEXHOME
+ bool "GoFlex Home Board"
+
+config TARGET_NAS220
+ bool "BlackArmor NAS220"
+
+endchoice
+
+config SYS_SOC
+ default "kirkwood"
+
+source "board/Marvell/openrd/Kconfig"
+source "board/Marvell/mv88f6281gtw_ge/Kconfig"
+source "board/Marvell/rd6281a/Kconfig"
+source "board/Marvell/dreamplug/Kconfig"
+source "board/Marvell/guruplug/Kconfig"
+source "board/Marvell/sheevaplug/Kconfig"
+source "board/buffalo/lsxl/Kconfig"
+source "board/cloudengines/pogo_e02/Kconfig"
+source "board/d-link/dns325/Kconfig"
+source "board/iomega/iconnect/Kconfig"
+source "board/karo/tk71/Kconfig"
+source "board/keymile/km_arm/Kconfig"
+source "board/LaCie/net2big_v2/Kconfig"
+source "board/LaCie/netspace_v2/Kconfig"
+source "board/LaCie/wireless_space/Kconfig"
+source "board/raidsonic/ib62x0/Kconfig"
+source "board/Seagate/dockstar/Kconfig"
+source "board/Seagate/goflexhome/Kconfig"
+source "board/Seagate/nas220/Kconfig"
+
+endif
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
new file mode 100644
index 0000000..df4756e
--- /dev/null
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = cpu.o
+obj-y += cache.o
+obj-y += mpp.o
diff --git a/arch/arm/mach-kirkwood/cache.c b/arch/arm/mach-kirkwood/cache.c
new file mode 100644
index 0000000..e18a309
--- /dev/null
+++ b/arch/arm/mach-kirkwood/cache.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2012 Michael Walle
+ * Michael Walle <michael@walle.cc>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/arch/cpu.h>
+
+#define FEROCEON_EXTRA_FEATURE_L2C_EN (1<<22)
+
+void l2_cache_disable()
+{
+ u32 ctrl;
+
+ ctrl = readfr_extra_feature_reg();
+ ctrl &= ~FEROCEON_EXTRA_FEATURE_L2C_EN;
+ writefr_extra_feature_reg(ctrl);
+}
diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c
new file mode 100644
index 0000000..4c9d3fd
--- /dev/null
+++ b/arch/arm/mach-kirkwood/cpu.c
@@ -0,0 +1,321 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/cache.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <mvebu_mmc.h>
+
+void reset_cpu(unsigned long ignored)
+{
+ struct kwcpu_registers *cpureg =
+ (struct kwcpu_registers *)KW_CPU_REG_BASE;
+
+ writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
+ &cpureg->rstoutn_mask);
+ writel(readl(&cpureg->sys_soft_rst) | 1,
+ &cpureg->sys_soft_rst);
+ while (1) ;
+}
+
+/*
+ * Window Size
+ * Used with the Base register to set the address window size and location.
+ * Must be programmed from LSB to MSB as sequence of ones followed by
+ * sequence of zeros. The number of ones specifies the size of the window in
+ * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
+ * NOTE: A value of 0x0 specifies 64-KByte size.
+ */
+unsigned int kw_winctrl_calcsize(unsigned int sizeval)
+{
+ int i;
+ unsigned int j = 0;
+ u32 val = sizeval >> 1;
+
+ for (i = 0; val >= 0x10000; i++) {
+ j |= (1 << i);
+ val = val >> 1;
+ }
+ return (0x0000ffff & j);
+}
+
+/*
+ * kw_config_adr_windows - Configure address Windows
+ *
+ * There are 8 address windows supported by Kirkwood Soc to addess different
+ * devices. Each window can be configured for size, BAR and remap addr
+ * Below configuration is standard for most of the cases
+ *
+ * If remap function not used, remap_lo must be set as base
+ *
+ * Reference Documentation:
+ * Mbus-L to Mbus Bridge Registers Configuration.
+ * (Sec 25.1 and 25.3 of Datasheet)
+ */
+int kw_config_adr_windows(void)
+{
+ struct kwwin_registers *winregs =
+ (struct kwwin_registers *)KW_CPU_WIN_BASE;
+
+ /* Window 0: PCIE MEM address space */
+ writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE,
+ KWCPU_ATTR_PCIE_MEM, KWCPU_WIN_ENABLE), &winregs[0].ctrl);
+
+ writel(KW_DEFADR_PCI_MEM, &winregs[0].base);
+ writel(KW_DEFADR_PCI_MEM, &winregs[0].remap_lo);
+ writel(0x0, &winregs[0].remap_hi);
+
+ /* Window 1: PCIE IO address space */
+ writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE,
+ KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl);
+ writel(KW_DEFADR_PCI_IO, &winregs[1].base);
+ writel(KW_DEFADR_PCI_IO_REMAP, &winregs[1].remap_lo);
+ writel(0x0, &winregs[1].remap_hi);
+
+ /* Window 2: NAND Flash address space */
+ writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
+ KWCPU_ATTR_NANDFLASH, KWCPU_WIN_ENABLE), &winregs[2].ctrl);
+ writel(KW_DEFADR_NANDF, &winregs[2].base);
+ writel(KW_DEFADR_NANDF, &winregs[2].remap_lo);
+ writel(0x0, &winregs[2].remap_hi);
+
+ /* Window 3: SPI Flash address space */
+ writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
+ KWCPU_ATTR_SPIFLASH, KWCPU_WIN_ENABLE), &winregs[3].ctrl);
+ writel(KW_DEFADR_SPIF, &winregs[3].base);
+ writel(KW_DEFADR_SPIF, &winregs[3].remap_lo);
+ writel(0x0, &winregs[3].remap_hi);
+
+ /* Window 4: BOOT Memory address space */
+ writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
+ KWCPU_ATTR_BOOTROM, KWCPU_WIN_ENABLE), &winregs[4].ctrl);
+ writel(KW_DEFADR_BOOTROM, &winregs[4].base);
+
+ /* Window 5: Security SRAM address space */
+ writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM,
+ KWCPU_ATTR_SASRAM, KWCPU_WIN_ENABLE), &winregs[5].ctrl);
+ writel(KW_DEFADR_SASRAM, &winregs[5].base);
+
+ /* Window 6-7: Disabled */
+ writel(KWCPU_WIN_DISABLE, &winregs[6].ctrl);
+ writel(KWCPU_WIN_DISABLE, &winregs[7].ctrl);
+
+ return 0;
+}
+
+/*
+ * SYSRSTn Duration Counter Support
+ *
+ * Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
+ * When SYSRSTn is asserted low, a SYSRSTn duration counter is running.
+ * The SYSRSTn duration counter is useful for implementing a manufacturer
+ * or factory reset. Upon a long reset assertion that is greater than a
+ * pre-configured environment variable value for sysrstdelay,
+ * The counter value is stored in the SYSRSTn Length Counter Register
+ * The counter is based on the 25-MHz reference clock (40ns)
+ * It is a 29-bit counter, yielding a maximum counting duration of
+ * 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value,
+ * it remains at this value until counter reset is triggered by setting
+ * bit 31 of KW_REG_SYSRST_CNT
+ */
+static void kw_sysrst_action(void)
+{
+ int ret;
+ char *s = getenv("sysrstcmd");
+
+ if (!s) {
+ debug("Error.. %s failed, check sysrstcmd\n",
+ __FUNCTION__);
+ return;
+ }
+
+ debug("Starting %s process...\n", __FUNCTION__);
+ ret = run_command(s, 0);
+ if (ret != 0)
+ debug("Error.. %s failed\n", __FUNCTION__);
+ else
+ debug("%s process finished\n", __FUNCTION__);
+}
+
+static void kw_sysrst_check(void)
+{
+ u32 sysrst_cnt, sysrst_dly;
+ char *s;
+
+ /*
+ * no action if sysrstdelay environment variable is not defined
+ */
+ s = getenv("sysrstdelay");
+ if (s == NULL)
+ return;
+
+ /* read sysrstdelay value */
+ sysrst_dly = (u32) simple_strtoul(s, NULL, 10);
+
+ /* read SysRst Length counter register (bits 28:0) */
+ sysrst_cnt = (0x1fffffff & readl(KW_REG_SYSRST_CNT));
+ debug("H/w Rst hold time: %d.%d secs\n",
+ sysrst_cnt / SYSRST_CNT_1SEC_VAL,
+ sysrst_cnt % SYSRST_CNT_1SEC_VAL);
+
+ /* clear the counter for next valid read*/
+ writel(1 << 31, KW_REG_SYSRST_CNT);
+
+ /*
+ * sysrst_action:
+ * if H/w Reset key is pressed and hold for time
+ * more than sysrst_dly in seconds
+ */
+ if (sysrst_cnt >= SYSRST_CNT_1SEC_VAL * sysrst_dly)
+ kw_sysrst_action();
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ char *rev = "??";
+ u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
+ u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
+
+ if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) {
+ printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid);
+ return -1;
+ }
+
+ switch (revid) {
+ case 0:
+ if (devid == 0x6281)
+ rev = "Z0";
+ else if (devid == 0x6282)
+ rev = "A0";
+ break;
+ case 1:
+ rev = "A1";
+ break;
+ case 2:
+ rev = "A0";
+ break;
+ case 3:
+ rev = "A1";
+ break;
+ default:
+ break;
+ }
+
+ printf("SoC: Kirkwood 88F%04x_%s\n", devid, rev);
+ return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+ u32 reg;
+ struct kwcpu_registers *cpureg =
+ (struct kwcpu_registers *)KW_CPU_REG_BASE;
+
+ /* Linux expects` the internal registers to be at 0xf1000000 */
+ writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);
+
+ /* Enable and invalidate L2 cache in write through mode */
+ writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
+ invalidate_l2_cache();
+
+ kw_config_adr_windows();
+
+#ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
+ /*
+ * Configures the I/O voltage of the pads connected to Egigabit
+ * Ethernet interface to 1.8V
+ * By default it is set to 3.3V
+ */
+ reg = readl(KW_REG_MPP_OUT_DRV_REG);
+ reg |= (1 << 7);
+ writel(reg, KW_REG_MPP_OUT_DRV_REG);
+#endif
+#ifdef CONFIG_KIRKWOOD_EGIGA_INIT
+ /*
+ * Set egiga port0/1 in normal functional mode
+ * This is required becasue on kirkwood by default ports are in reset mode
+ * OS egiga driver may not have provision to set them in normal mode
+ * and if u-boot is build without network support, network may fail at OS level
+ */
+ reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0));
+ reg &= ~(1 << 4); /* Clear PortReset Bit */
+ writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0)));
+ reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1));
+ reg &= ~(1 << 4); /* Clear PortReset Bit */
+ writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1)));
+#endif
+#ifdef CONFIG_KIRKWOOD_PCIE_INIT
+ /*
+ * Enable PCI Express Port0
+ */
+ reg = readl(&cpureg->ctrl_stat);
+ reg |= (1 << 0); /* Set PEX0En Bit */
+ writel(reg, &cpureg->ctrl_stat);
+#endif
+ return 0;
+}
+#endif /* CONFIG_ARCH_CPU_INIT */
+
+/*
+ * SOC specific misc init
+ */
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+ volatile u32 temp;
+
+ /*CPU streaming & write allocate */
+ temp = readfr_extra_feature_reg();
+ temp &= ~(1 << 28); /* disable wr alloc */
+ writefr_extra_feature_reg(temp);
+
+ temp = readfr_extra_feature_reg();
+ temp &= ~(1 << 29); /* streaming disabled */
+ writefr_extra_feature_reg(temp);
+
+ /* L2Cache settings */
+ temp = readfr_extra_feature_reg();
+ /* Disable L2C pre fetch - Set bit 24 */
+ temp |= (1 << 24);
+ /* enable L2C - Set bit 22 */
+ temp |= (1 << 22);
+ writefr_extra_feature_reg(temp);
+
+ icache_enable();
+ /* Change reset vector to address 0x0 */
+ temp = get_cr();
+ set_cr(temp & ~CR_V);
+
+ /* checks and execute resset to factory event */
+ kw_sysrst_check();
+
+ return 0;
+}
+#endif /* CONFIG_ARCH_MISC_INIT */
+
+#ifdef CONFIG_MVGBE
+int cpu_eth_init(bd_t *bis)
+{
+ mvgbe_initialize(bis);
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_MVEBU_MMC
+int board_mmc_init(bd_t *bis)
+{
+ mvebu_mmc_init(bis);
+ return 0;
+}
+#endif /* CONFIG_MVEBU_MMC */
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
new file mode 100644
index 0000000..7222504
--- /dev/null
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -0,0 +1,90 @@
+/*
+ * arch/arm/mach-kirkwood/mpp.c
+ *
+ * MPP functions for Marvell Kirkwood SoCs
+ * Referenced from Linux kernel source
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+
+static u32 kirkwood_variant(void)
+{
+ switch (readl(KW_REG_DEVICE_ID) & 0x03) {
+ case 1:
+ return MPP_F6192_MASK;
+ case 2:
+ return MPP_F6281_MASK;
+ default:
+ debug("MPP setup: unknown kirkwood variant\n");
+ return 0;
+ }
+}
+
+#define MPP_CTRL(i) (KW_MPP_BASE + (i* 4))
+#define MPP_NR_REGS (1 + MPP_MAX/8)
+
+void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save)
+{
+ u32 mpp_ctrl[MPP_NR_REGS];
+ unsigned int variant_mask;
+ int i;
+
+ variant_mask = kirkwood_variant();
+ if (!variant_mask)
+ return;
+
+ debug( "initial MPP regs:");
+ for (i = 0; i < MPP_NR_REGS; i++) {
+ mpp_ctrl[i] = readl(MPP_CTRL(i));
+ debug(" %08x", mpp_ctrl[i]);
+ }
+ debug("\n");
+
+
+ while (*mpp_list) {
+ unsigned int num = MPP_NUM(*mpp_list);
+ unsigned int sel = MPP_SEL(*mpp_list);
+ unsigned int sel_save;
+ int shift;
+
+ if (num > MPP_MAX) {
+ debug("kirkwood_mpp_conf: invalid MPP "
+ "number (%u)\n", num);
+ continue;
+ }
+ if (!(*mpp_list & variant_mask)) {
+ debug("kirkwood_mpp_conf: requested MPP%u config "
+ "unavailable on this hardware\n", num);
+ continue;
+ }
+
+ shift = (num & 7) << 2;
+
+ if (mpp_save) {
+ sel_save = (mpp_ctrl[num / 8] >> shift) & 0xf;
+ *mpp_save = num | (sel_save << 8) | variant_mask;
+ mpp_save++;
+ }
+
+ mpp_ctrl[num / 8] &= ~(0xf << shift);
+ mpp_ctrl[num / 8] |= sel << shift;
+
+ mpp_list++;
+ }
+
+ debug(" final MPP regs:");
+ for (i = 0; i < MPP_NR_REGS; i++) {
+ writel(mpp_ctrl[i], MPP_CTRL(i));
+ debug(" %08x", mpp_ctrl[i]);
+ }
+ debug("\n");
+
+}