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authorLokesh Vutla <lokeshvutla@ti.com>2015-07-28 14:16:45 +0530
committerTom Rini <trini@konsulko.com>2015-08-12 20:47:53 -0400
commit74af583e9f7a255443d8f625c8dce6da7b9703be (patch)
treefbd63bb5fad0a796a8dcfcf4cfca0623fa235f17 /arch/arm/mach-keystone/include/mach/hardware-k2hk.h
parent7b50e1599f4e6551a3348ca5f061a596f6f6896e (diff)
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ARM: keystone2: Use common structure for PLLs
Register Base addresses are same for PLLs in all keystone platforms. If a PLL is not available, the corresponding register addresses are marked as reserved. Hence use a common definition. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/mach-keystone/include/mach/hardware-k2hk.h')
-rw-r--r--arch/arm/mach-keystone/include/mach/hardware-k2hk.h4
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2hk.h b/arch/arm/mach-keystone/include/mach/hardware-k2hk.h
index 195c0d3..8c771dc 100644
--- a/arch/arm/mach-keystone/include/mach/hardware-k2hk.h
+++ b/arch/arm/mach-keystone/include/mach/hardware-k2hk.h
@@ -15,10 +15,6 @@
/* PA SS Registers */
#define KS2_PASS_BASE 0x02000000
-/* PLL control registers */
-#define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
-#define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
-
/* Power and Sleep Controller (PSC) Domains */
#define KS2_LPSC_MOD 0
#define KS2_LPSC_DUMMY1 1