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author | Masahiro Yamada <yamada.m@jp.panasonic.com> | 2015-02-20 17:04:13 +0900 |
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committer | Tom Rini <trini@ti.com> | 2015-02-21 08:23:52 -0500 |
commit | af9308276028924ff7f84770ddbd26bd7046d6c5 (patch) | |
tree | 55f2467ec5635acc83c97a92df33036f414d9f1f /arch/arm/mach-at91/include/mach/sama5_sfr.h | |
parent | 0e7368c6c4265c138293802b3315629338bc66d0 (diff) | |
download | u-boot-imx-af9308276028924ff7f84770ddbd26bd7046d6c5.zip u-boot-imx-af9308276028924ff7f84770ddbd26bd7046d6c5.tar.gz u-boot-imx-af9308276028924ff7f84770ddbd26bd7046d6c5.tar.bz2 |
ARM: at91: move SoC headers to mach-at91/include/mach
Move arch/arm/include/asm/arch-at91/*
-> arch/arm/mach-at91/include/mach/*
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
Diffstat (limited to 'arch/arm/mach-at91/include/mach/sama5_sfr.h')
-rw-r--r-- | arch/arm/mach-at91/include/mach/sama5_sfr.h | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/include/mach/sama5_sfr.h b/arch/arm/mach-at91/include/mach/sama5_sfr.h new file mode 100644 index 0000000..3081d37 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sama5_sfr.h @@ -0,0 +1,38 @@ +/* + * Special Function Register (SFR) + * + * Copyright (C) 2014 Atmel + * Bo Shen <voice.shen@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SAMA5_SFR_H +#define __SAMA5_SFR_H + +struct atmel_sfr { + u32 reserved1; /* 0x00 */ + u32 ddrcfg; /* 0x04: DDR Configuration Register */ + u32 reserved2; /* 0x08 */ + u32 reserved3; /* 0x0c */ + u32 ohciicr; /* 0x10: OHCI Interrupt Configuration Register */ + u32 ohciisr; /* 0x14: OHCI Interrupt Status Register */ + u32 reserved4[4]; /* 0x18 ~ 0x24 */ + u32 secure; /* 0x28: Security Configuration Register */ + u32 reserved5[5]; /* 0x2c ~ 0x3c */ + u32 ebicfg; /* 0x40: EBI Configuration Register */ + u32 reserved6[2]; /* 0x44 ~ 0x48 */ + u32 sn0; /* 0x4c */ + u32 sn1; /* 0x50 */ + u32 aicredir; /* 0x54 */ +}; + +/* Bit field in DDRCFG */ +#define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000 +#define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000 + +/* Bit field in AICREDIR */ +#define ATMEL_SFR_AICREDIR_KEY 0x5F67B102 +#define ATMEL_SFR_AICREDIR_NSAIC 0x00000001 + +#endif |