diff options
author | Andre Przywara <andre.przywara@linaro.org> | 2013-09-19 18:06:42 +0200 |
---|---|---|
committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-10-03 21:28:43 +0200 |
commit | 1ef923851ab8ffcc4265fd991815b88d9c1f12d7 (patch) | |
tree | 4d23688d7fd04f205bb410069788f3032bd186c0 /arch/arm/lib | |
parent | 16212b594f385bd594d5d316bf11b13c1186e3d7 (diff) | |
download | u-boot-imx-1ef923851ab8ffcc4265fd991815b88d9c1f12d7.zip u-boot-imx-1ef923851ab8ffcc4265fd991815b88d9c1f12d7.tar.gz u-boot-imx-1ef923851ab8ffcc4265fd991815b88d9c1f12d7.tar.bz2 |
ARM: add C function to switch to non-secure state
The core specific part of the work is done in the assembly routine
in nonsec_virt.S, introduced with the previous patch, but for the full
glory we need to setup the GIC distributor interface once for the
whole system, which is done in C here.
The routine is placed in arch/arm/cpu/armv7 to allow easy access from
other ARMv7 boards.
We check the availability of the security extensions first.
Since we need a safe way to access the GIC, we use the PERIPHBASE
registers on Cortex-A15 and A7 CPUs and do some sanity checks.
Boards not implementing the CBAR can override this value via a
configuration file variable.
Then we actually do the GIC enablement:
a) enable the GIC distributor, both for non-secure and secure state
(GICD_CTLR[1:0] = 11b)
b) allow all interrupts to be handled from non-secure state
(GICD_IGROUPRn = 0xFFFFFFFF)
The core specific GIC setup is then done in the assembly routine.
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
Diffstat (limited to 'arch/arm/lib')
0 files changed, 0 insertions, 0 deletions