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| author | York Sun <yorksun@freescale.com> | 2014-09-08 12:20:00 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-09-25 08:36:19 -0700 |
| commit | 40f8dec54d7803975aed1c88327002c95ea99908 (patch) | |
| tree | 83f7778c9179e518631ce308f3504a1e6e634c57 /arch/arm/lib | |
| parent | f43b4356a794be647011132f4f2dc970a29a9dd5 (diff) | |
| download | u-boot-imx-40f8dec54d7803975aed1c88327002c95ea99908.zip u-boot-imx-40f8dec54d7803975aed1c88327002c95ea99908.tar.gz u-boot-imx-40f8dec54d7803975aed1c88327002c95ea99908.tar.bz2 | |
armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page
Secondary cores need to be released from holdoff by boot release
registers. With GPP bootrom, they can boot from main memory
directly. Individual spin table is used for each core. Spin table
and the boot page is reserved in device tree so OS won't overwrite.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
Diffstat (limited to 'arch/arm/lib')
| -rw-r--r-- | arch/arm/lib/gic_64.S | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/arch/arm/lib/gic_64.S b/arch/arm/lib/gic_64.S index d56396e..a3e18f7 100644 --- a/arch/arm/lib/gic_64.S +++ b/arch/arm/lib/gic_64.S @@ -10,8 +10,8 @@ #include <asm-offsets.h> #include <config.h> #include <linux/linkage.h> -#include <asm/macro.h> #include <asm/gic.h> +#include <asm/macro.h> /************************************************************************* @@ -181,14 +181,10 @@ ENDPROC(gic_kick_secondary_cpus) * *************************************************************************/ ENTRY(gic_wait_for_interrupt) -0: wfi #if defined(CONFIG_GICV3) - mrs x9, ICC_IAR1_EL1 - msr ICC_EOIR1_EL1, x9 + gic_wait_for_interrupt_m x9 #elif defined(CONFIG_GICV2) - ldr w9, [x0, GICC_AIAR] - str w9, [x0, GICC_AEOIR] + gic_wait_for_interrupt_m x0, w9 #endif - cbnz w9, 0b ret ENDPROC(gic_wait_for_interrupt) |