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authorHeiko Schocher <hs@denx.de>2014-11-18 09:41:56 +0100
committerAndreas Bießmann <andreas.devel@googlemail.com>2015-01-19 12:49:26 +0100
commit99197a9e316cbedd315135fcfd7673221a746df7 (patch)
tree6eb0b781b3ace1f14134ffe2542b4c3b8779ca0f /arch/arm/lib
parentab77f24119e80257de4ab017b877f92f96980562 (diff)
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arm, arm926ejs: make thumb mode compileable
in thumb mode compiler says for example for arch/arm/lib/cache-cp15.c when enabling CONFIG_SYS_THUMB_BUILD: {standard input}: Assembler messages: {standard input}:373: Error: selected processor does not support Thumb mode `mrc p15,0,r4,c1,c0,0' {standard input}:416: Error: selected processor does not support Thumb mode `mcr p15,0,r3,c2,c0,0' so, if caches are disabled, do not use this command on arm926ejs. used on at91 in SPL, to reduce size of SPL. Signed-off-by: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'arch/arm/lib')
-rw-r--r--arch/arm/lib/cache.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 9cedeac..74cfde6 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -25,10 +25,12 @@ __weak void flush_cache(unsigned long start, unsigned long size)
#endif /* CONFIG_CPU_ARM1136 */
#ifdef CONFIG_CPU_ARM926EJS
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
/* test and clean, page 2-23 of arm926ejs manual */
asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
/* disable write buffer as well (page 2-22) */
asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+#endif
#endif /* CONFIG_CPU_ARM926EJS */
return;
}