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authorThierry Reding <treding@nvidia.com>2014-08-26 17:34:21 +0200
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-11-12 07:25:42 +0100
commit25026fa9f16dd5f9182b47f76ce5043cb35da3f4 (patch)
tree987555c18dc82693c3d7946300e9afcab4721d81 /arch/arm/lib/cache-cp15.c
parentb9297c22661437aa57281d9e4f901a7f6c6b6f12 (diff)
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ARM: cache-cp15: Use more accurate types
size_t is the canonical type to represent variables that contain a size. Use it instead of signed integer. Physical addresses can be larger than 32-bit, so use a more appropriate type for them as well. phys_addr_t is a type that is 32-bit on systems that use 32-bit addresses and 64-bit if the system is 64-bit or uses a form of physical address extension to use a larger address space on 32-bit systems. Using these types the same API can be implemented on a wider range of systems. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/lib/cache-cp15.c')
-rw-r--r--arch/arm/lib/cache-cp15.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 2155fe8..0291afa 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -47,15 +47,15 @@ __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
debug("%s: Warning: not implemented\n", __func__);
}
-void mmu_set_region_dcache_behaviour(u32 start, int size,
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
enum dcache_option option)
{
u32 *page_table = (u32 *)gd->arch.tlb_addr;
- u32 upto, end;
+ unsigned long upto, end;
end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
start = start >> MMU_SECTION_SHIFT;
- debug("%s: start=%x, size=%x, option=%d\n", __func__, start, size,
+ debug("%s: start=%pa, size=%zu, option=%d\n", __func__, &start, size,
option);
for (upto = start; upto < end; upto++)
set_section_dcache(upto, option);