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| author | Alim Akhtar <alim.akhtar@samsung.com> | 2014-11-13 22:38:18 +0530 |
|---|---|---|
| committer | Minkyu Kang <mk7.kang@samsung.com> | 2014-11-17 19:03:38 +0900 |
| commit | 061091098a5ec55ff4b68b61592af8619c2c7d88 (patch) | |
| tree | b5339bc118f1e114d79713dc0e6bf5022e025085 /arch/arm/include | |
| parent | 79043d84da076e4eb47e04495c55216897c9a161 (diff) | |
| download | u-boot-imx-061091098a5ec55ff4b68b61592af8619c2c7d88.zip u-boot-imx-061091098a5ec55ff4b68b61592af8619c2c7d88.tar.gz u-boot-imx-061091098a5ec55ff4b68b61592af8619c2c7d88.tar.bz2 | |
DMC: Exynos5: Enable update mode for DREX controller
As per Exynos5800 UM ver 0.00 section 17.13.2.1
CONCONTROL register bit 3 [update_mode], Exynos5800 does not
support the PHY initiated update. And it is recommanded to
set this field to 1'b1 during initialization. This patch sets this bit.
Applying MC-initiated mode makes DDL tracking ON, that helps in
compensate MIF voltage variation.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-exynos/dmc.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h index ec3f9b6..4990a1a 100644 --- a/arch/arm/include/asm/arch-exynos/dmc.h +++ b/arch/arm/include/asm/arch-exynos/dmc.h @@ -450,6 +450,7 @@ enum mem_manuf { #define CONCONTROL_RD_FETCH_SHIFT 12 #define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT) #define CONCONTROL_AREF_EN_SHIFT 5 +#define CONCONTROL_UPDATE_MODE (1 << 3) /* PRECHCONFIG register field */ #define PRECHCONFIG_TP_CNT_SHIFT 24 |