diff options
| author | Haikun Wang <Haikun.Wang@freescale.com> | 2015-06-26 19:58:12 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-07-20 11:44:39 -0700 |
| commit | e71a980a4d4eb01bc3eb7624fc59cd8f999bf4b2 (patch) | |
| tree | 5ff6c59571d8ed24769bf2a345c9e0c6a87555a3 /arch/arm/include | |
| parent | b0e209dc636d76afa90e330c37d29cea6deeea33 (diff) | |
| download | u-boot-imx-e71a980a4d4eb01bc3eb7624fc59cd8f999bf4b2.zip u-boot-imx-e71a980a4d4eb01bc3eb7624fc59cd8f999bf4b2.tar.gz u-boot-imx-e71a980a4d4eb01bc3eb7624fc59cd8f999bf4b2.tar.bz2 | |
armv8/ls2085aqds: DSPI pin muxing configure through QIXIS
DSPI has pin muxing with SDHC and other IPs, this patch check the
value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check
the "hwconfig" variable. If those pins are configured to DSPI and
"hwconfig" enable DSPI, set the BRDCFG5 of QIXIS FPGA to configure
the routing to on-board SPI memory. Otherwise will configure to SDHC.
DSPI is enabled in "hwconfig" by appending "dspi", eg.
setenv hwconfig "$hwconfig;dspi"
Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-lsch3/config.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index ca8d38c..8675e91 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -137,6 +137,8 @@ #define DCFG_PORSR1 0x000 #define DCFG_PORSR1_RCW_SRC 0xff800000 #define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000 +#define DCFG_RCWSR13 0x130 +#define DCFG_RCWSR13_DSPI (0 << 8) #define DCFG_DCSR_BASE 0X700100000ULL #define DCFG_DCSR_PORCR1 0x000 |