diff options
| author | Michal Simek <monstr@monstr.eu> | 2012-10-15 14:01:23 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2013-04-30 11:39:19 +0200 |
| commit | 80243528efa5e17db60328005344bb8a5e8e8076 (patch) | |
| tree | 8dbcc857b681a640ebd90eb7ec8f11daa003668c /arch/arm/include | |
| parent | 058687597d3ff26c415db33614b881de258a365b (diff) | |
| download | u-boot-imx-80243528efa5e17db60328005344bb8a5e8e8076.zip u-boot-imx-80243528efa5e17db60328005344bb8a5e8e8076.tar.gz u-boot-imx-80243528efa5e17db60328005344bb8a5e8e8076.tar.bz2 | |
net: gem: Fix gem driver on 1Gbps LAN
The whole driver used 100Mbps because of zc702 rev B.
Fix problem with not setup proper clock for gem1.
This is generic approach for clk setup.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-zynq/hardware.h | 7 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-zynq/sys_proto.h | 1 |
2 files changed, 7 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h index ccbf54e..d8e378f 100644 --- a/arch/arm/include/asm/arch-zynq/hardware.h +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -33,7 +33,12 @@ struct slcr_regs { u32 scl; /* 0x0 */ u32 slcr_lock; /* 0x4 */ u32 slcr_unlock; /* 0x8 */ - u32 reserved1[125]; + u32 reserved0[75]; + u32 gem0_rclk_ctrl; /* 0x138 */ + u32 gem1_rclk_ctrl; /* 0x13c */ + u32 gem0_clk_ctrl; /* 0x140 */ + u32 gem1_clk_ctrl; /* 0x144 */ + u32 reserved1[46]; u32 pss_rst_ctrl; /* 0x200 */ u32 reserved2[15]; u32 fpga_rst_ctrl; /* 0x240 */ diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h index e788900..57128dc 100644 --- a/arch/arm/include/asm/arch-zynq/sys_proto.h +++ b/arch/arm/include/asm/arch-zynq/sys_proto.h @@ -26,5 +26,6 @@ extern void zynq_slcr_lock(void); extern void zynq_slcr_unlock(void); extern void zynq_slcr_cpu_reset(void); +extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk); #endif /* _SYS_PROTO_H_ */ |