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authorFabio Estevam <fabio.estevam@freescale.com>2014-04-29 10:15:46 -0300
committerStefano Babic <sbabic@denx.de>2014-05-09 15:10:53 +0200
commit98d2cffd23503225108e0ceb36dbe6b1bbd93ed6 (patch)
tree2607681c73e535c3993c9f26d333d2ea3a87c87b /arch/arm/include
parent234d89dac61a4f57a0f7cb136a6c442f37a6c9b8 (diff)
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iomux-v3: Add support for mx6sl LVE bit
On mx6sl there is a LVE (Low Voltage Enable) bit in the IOMUXC_SW_PAD_CTL register that can enable or disable low voltage on the pad. LVE is bit 22 of IOMUXC_SW_PAD_CTL register, but in order to make the calculation easier we can define it as a flag in bit 1, since this bit is unused. Add support for it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Otavio Salvador <otavio@ossystems.com.br>
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/imx-common/iomux-v3.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h
index dec11a1..cca920b 100644
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -111,6 +111,11 @@ typedef u64 iomux_v3_cfg_t;
#define PAD_CTL_DSE_40ohm (6 << 3)
#define PAD_CTL_DSE_34ohm (7 << 3)
+#if defined CONFIG_MX6SL
+#define PAD_CTL_LVE (1 << 1)
+#define PAD_CTL_LVE_BIT (1 << 22)
+#endif
+
#elif defined(CONFIG_VF610)
#define PAD_MUX_MODE_SHIFT 20