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authorXiubo Li <Li.Xiubo@freescale.com>2014-11-21 17:40:59 +0800
committerYork Sun <yorksun@freescale.com>2014-12-11 09:42:22 -0800
commit660673af4fd10c544ceeedeb524ba92c27dbc586 (patch)
tree2979c885f915d9aa5561a7977ac2c1b3543aa0ff /arch/arm/include
parente87f3b308c454f6e78b02da857936c7d012c385b (diff)
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ARM: ls102xa: Setting device's stream id for SMMUs.
LS1 has 4 SMMUs for address translation of the masters. All the SMMUs' stream IDs are 8-bit. The address translation depends on the stream ID of the incoming transaction. Each master has unique stream ID assigned to it and is configurable through SCFG registers. The stream ID for the masters is identical and share the same register field of STREAM ID registers. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h17
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
new file mode 100644
index 0000000..abd70fc
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSL_LS102XA_STREAM_ID_H_
+#define __FSL_LS102XA_STREAM_ID_H_
+
+struct smmu_stream_id {
+ uint16_t offset;
+ uint16_t stream_id;
+ char dev_name[32];
+};
+
+void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num);
+#endif