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authorpekon gupta <pekon@ti.com>2013-11-18 19:03:02 +0530
committerScott Wood <scottwood@freescale.com>2013-11-21 13:33:41 -0600
commit2c17e6d1d996a1b8b9325de15f253a13d5877dee (patch)
tree5404e5dea7c6e046fdaaa07fa98f4231c6fc1340 /arch/arm/include
parent3f719069c884284b2457448a7afe32b02bd4f782 (diff)
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am335x: fix GPMC config for NAND and NOR SPL boot
GPMC controller is common IP to interface with both NAND and NOR flash devices. Also, it supports max 8 chip-selects, which can be independently connected to any of the devices. But ROM code expects the boot-device to be connected to only chip-select[0]. Thus to resolve conflict between NOR and NAND boot. This patch: - combines NOR and NAND configs spread in board files to common gpmc_init() - configures GPMC based on boot-mode selected for SPL boot. Signed-off-by: Pekon Gupta <pekon@ti.com>
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/arch-am33xx/mem.h5
1 files changed, 0 insertions, 5 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/mem.h b/arch/arm/include/asm/arch-am33xx/mem.h
index 983ea28..e7e8c58 100644
--- a/arch/arm/include/asm/arch-am33xx/mem.h
+++ b/arch/arm/include/asm/arch-am33xx/mem.h
@@ -68,9 +68,4 @@
#define PISMO2_NAND_CS0 7
#define PISMO2_NAND_CS1 8
-/* make it readable for the gpmc_init */
-#define PISMO1_NOR_BASE FLASH_BASE
-#define PISMO1_NAND_BASE CONFIG_SYS_NAND_BASE
-#define PISMO1_NAND_SIZE GPMC_SIZE_256M
-
#endif /* endif _MEM_H_ */