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| author | Mathieu J. Poirier <mathieu.poirier@linaro.org> | 2012-07-31 08:59:25 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-09-01 14:58:19 +0200 |
| commit | 9652de7c488c4915c91626b71fa553d3ed13da47 (patch) | |
| tree | 7b2df3cf96717fdc8c2938bb228b683f9a8f9136 /arch/arm/include | |
| parent | 42cb8fb6cb2c869229b0158e3c86c50fb242d6aa (diff) | |
| download | u-boot-imx-9652de7c488c4915c91626b71fa553d3ed13da47.zip u-boot-imx-9652de7c488c4915c91626b71fa553d3ed13da47.tar.gz u-boot-imx-9652de7c488c4915c91626b71fa553d3ed13da47.tar.bz2 | |
snowball: Adding architecture dependent initialisation
Enabling timers and clocks in PRCMU and cleaning up mailbox.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-u8500/prcmu.h | 24 |
1 files changed, 19 insertions, 5 deletions
diff --git a/arch/arm/include/asm/arch-u8500/prcmu.h b/arch/arm/include/asm/arch-u8500/prcmu.h index 0836983..1fd4d2a 100644 --- a/arch/arm/include/asm/arch-u8500/prcmu.h +++ b/arch/arm/include/asm/arch-u8500/prcmu.h @@ -27,12 +27,23 @@ #define I2C_RD_OK 2 #define I2CWRITE 0 -#define _PRCMU_TCDM_BASE U8500_PRCMU_TCDM_BASE -#define PRCM_XP70_CUR_PWR_STATE (_PRCMU_TCDM_BASE + 0xFFC) /* 4 BYTES */ - -#define PRCM_REQ_MB5 (_PRCMU_TCDM_BASE + 0xE44) /* 4 bytes */ -#define PRCM_ACK_MB5 (_PRCMU_TCDM_BASE + 0xDF4) /* 4 bytes */ +#define PRCMU_BASE U8500_PRCMU_BASE +#define PRCM_UARTCLK_MGT_REG (PRCMU_BASE + 0x018) +#define PRCM_MSPCLK_MGT_REG (PRCMU_BASE + 0x01C) +#define PRCM_I2CCLK_MGT_REG (PRCMU_BASE + 0x020) +#define PRCM_SDMMCCLK_MGT_REG (PRCMU_BASE + 0x024) +#define PRCM_PER1CLK_MGT_REG (PRCMU_BASE + 0x02C) +#define PRCM_PER2CLK_MGT_REG (PRCMU_BASE + 0x030) +#define PRCM_PER3CLK_MGT_REG (PRCMU_BASE + 0x034) +#define PRCM_PER5CLK_MGT_REG (PRCMU_BASE + 0x038) +#define PRCM_PER6CLK_MGT_REG (PRCMU_BASE + 0x03C) +#define PRCM_PER7CLK_MGT_REG (PRCMU_BASE + 0x040) +#define PRCM_ARM_IT1_CLEAR (PRCMU_BASE + 0x48C) +#define PRCM_TCR (PRCMU_BASE + 0x1C8) +#define PRCM_REQ_MB5 (PRCMU_BASE + 0xE44) +#define PRCM_ACK_MB5 (PRCMU_BASE + 0xDF4) +#define PRCM_XP70_CUR_PWR_STATE (PRCMU_BASE + 0xFFC) /* Mailbox 5 Requests */ #define PRCM_REQ_MB5_I2COPTYPE_REG (PRCM_REQ_MB5 + 0x0) #define PRCM_REQ_MB5_BIT_FIELDS (PRCM_REQ_MB5 + 0x1) @@ -52,4 +63,7 @@ extern int prcmu_i2c_read(u8 reg, u16 slave); extern int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data); +void u8500_prcmu_enable(u32 *reg); +void db8500_prcmu_init(void); + #endif /* __MACH_PRCMU_FW_V1_H */ |