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| author | Darwin Rambo <drambo@broadcom.com> | 2014-02-11 11:06:34 -0800 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-02-22 19:30:24 +0100 |
| commit | 989ce049997daefc25c15e1d5bf5307cdca25abb (patch) | |
| tree | 52066caa3d0e37e471d7fd0c7a9dadf1d2329db6 /arch/arm/include | |
| parent | b3134fce890754ceb33fe79d7b0d8f78ee83129f (diff) | |
| download | u-boot-imx-989ce049997daefc25c15e1d5bf5307cdca25abb.zip u-boot-imx-989ce049997daefc25c15e1d5bf5307cdca25abb.tar.gz u-boot-imx-989ce049997daefc25c15e1d5bf5307cdca25abb.tar.bz2 | |
arch: bcm281xx: Initial commit of bcm281xx architecture code
Add bcm281xx architecture support code including a clock framework and
chip reset. Define register block base addresses for the bcm281xx
architecture and create an empty gpio header file required when
CONFIG_CMD_GPIO is set.
Signed-off-by: Darwin Rambo <drambo@broadcom.com>
Reviewed-by: Steve Rae <srae@broadcom.com>
Reviewed-by: Tim Kryger <tkryger@linaro.org>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-bcm281xx/gpio.h | 15 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-bcm281xx/sysmap.h | 25 |
2 files changed, 40 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-bcm281xx/gpio.h b/arch/arm/include/asm/arch-bcm281xx/gpio.h new file mode 100644 index 0000000..1b40a96 --- /dev/null +++ b/arch/arm/include/asm/arch-bcm281xx/gpio.h @@ -0,0 +1,15 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_BCM281XX_GPIO_H +#define __ARCH_BCM281XX_GPIO_H + +/* + * Empty file - cmd_gpio.c requires this. The implementation + * is in drivers/gpio/kona_gpio.c instead of inlined here. + */ + +#endif diff --git a/arch/arm/include/asm/arch-bcm281xx/sysmap.h b/arch/arm/include/asm/arch-bcm281xx/sysmap.h new file mode 100644 index 0000000..880b4e0 --- /dev/null +++ b/arch/arm/include/asm/arch-bcm281xx/sysmap.h @@ -0,0 +1,25 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_BCM281XX_SYSMAP_H + +#define BSC1_BASE_ADDR 0x3e016000 +#define BSC2_BASE_ADDR 0x3e017000 +#define BSC3_BASE_ADDR 0x3e018000 +#define GPIO2_BASE_ADDR 0x35003000 +#define KONA_MST_CLK_BASE_ADDR 0x3f001000 +#define KONA_SLV_CLK_BASE_ADDR 0x3e011000 +#define PMU_BSC_BASE_ADDR 0x3500d000 +#define PWRMGR_BASE_ADDR 0x35010000 +#define SDIO1_BASE_ADDR 0x3f180000 +#define SDIO2_BASE_ADDR 0x3f190000 +#define SDIO3_BASE_ADDR 0x3f1a0000 +#define SDIO4_BASE_ADDR 0x3f1b0000 +#define SECWD_BASE_ADDR 0x3500c000 +#define SECWD2_BASE_ADDR 0x35002f40 +#define TIMER_BASE_ADDR 0x3e00d000 + +#endif |