Merge branch 'master' into next

Conflicts:
	Makefile

Signed-off-by: Wolfgang Denk <wd@denx.de>

13 files changed, 1017 insertions, 2 deletions

diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index 81cc8ab..3520cf8 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -398,6 +398,7 @@ struct davinci_syscfg_regs {
 #define DAVINCI_SYSCFG_SUSPSRC_EMAC		(1 << 5)
 #define DAVINCI_SYSCFG_SUSPSRC_I2C		(1 << 16)
 #define DAVINCI_SYSCFG_SUSPSRC_SPI0		(1 << 21)
+#define DAVINCI_SYSCFG_SUSPSRC_SPI1		(1 << 22)
 #define DAVINCI_SYSCFG_SUSPSRC_UART2		(1 << 20)
 #define DAVINCI_SYSCFG_SUSPSRC_TIMER0		(1 << 27)
 
diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h
index aa8de32..c072c27 100644
--- a/arch/arm/include/asm/arch-omap3/cpu.h
+++ b/arch/arm/include/asm/arch-omap3/cpu.h
@@ -215,6 +215,31 @@ struct sdrc {
 	u8 res4[0xC];
 	struct sdrc_cs cs[2];	/* 0x80 || 0xB0 */
 };
+
+/* EMIF4 */
+typedef struct emif4 {
+	unsigned int sdram_sts;
+	unsigned int sdram_config;
+	unsigned int res1;
+	unsigned int sdram_refresh_ctrl;
+	unsigned int sdram_refresh_ctrl_shdw;
+	unsigned int sdram_time1;
+	unsigned int sdram_time1_shdw;
+	unsigned int sdram_time2;
+	unsigned int sdram_time2_shdw;
+	unsigned int sdram_time3;
+	unsigned int sdram_time3_shdw;
+	unsigned char res2[8];
+	unsigned int sdram_pwr_mgmt;
+	unsigned int sdram_pwr_mgmt_shdw;
+	unsigned char res3[32];
+	unsigned int sdram_iodft_tlgc;
+	unsigned char res4[128];
+	unsigned int ddr_phyctrl1;
+	unsigned int ddr_phyctrl1_shdw;
+	unsigned int ddr_phyctrl2;
+} emif4_t;
+
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL_STRICT_NAMES */
 
diff --git a/arch/arm/include/asm/arch-omap3/emif4.h b/arch/arm/include/asm/arch-omap3/emif4.h
new file mode 100644
index 0000000..579da0c
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap3/emif4.h
@@ -0,0 +1,79 @@
+/*
+ * Auther:
+ *       Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _EMIF_H_
+#define _EMIF_H_
+
+/*
+ * Configuration values
+ */
+#define EMIF4_TIM1_T_RP		(0x3 << 25)
+#define EMIF4_TIM1_T_RCD	(0x3 << 21)
+#define EMIF4_TIM1_T_WR		(0x3 << 17)
+#define EMIF4_TIM1_T_RAS	(0x8 << 12)
+#define EMIF4_TIM1_T_RC		(0xA << 6)
+#define EMIF4_TIM1_T_RRD	(0x2 << 3)
+#define EMIF4_TIM1_T_WTR	(0x2)
+
+#define EMIF4_TIM2_T_XP		(0x2 << 28)
+#define EMIF4_TIM2_T_ODT	(0x0 << 25)
+#define EMIF4_TIM2_T_XSNR	(0x1C << 16)
+#define EMIF4_TIM2_T_XSRD	(0xC8 << 6)
+#define EMIF4_TIM2_T_RTP	(0x1 << 3)
+#define EMIF4_TIM2_T_CKE	(0x2)
+
+#define EMIF4_TIM3_T_RFC	(0x25 << 4)
+#define EMIF4_TIM3_T_RAS_MAX	(0x7)
+
+#define EMIF4_PWR_IDLE_MODE	(0x2 << 30)
+#define EMIF4_PWR_DPD_DIS	(0x0 << 10)
+#define EMIF4_PWR_DPD_EN	(0x1 << 10)
+#define EMIF4_PWR_LP_MODE	(0x0 << 8)
+#define EMIF4_PWR_PM_TIM	(0x0)
+
+#define EMIF4_INITREF_DIS	(0x0 << 31)
+#define EMIF4_REFRESH_RATE	(0x50F)
+
+#define EMIF4_CFG_SDRAM_TYP	(0x2 << 29)
+#define EMIF4_CFG_IBANK_POS	(0x0 << 27)
+#define EMIF4_CFG_DDR_TERM	(0x0 << 24)
+#define EMIF4_CFG_DDR2_DDQS	(0x1 << 23)
+#define EMIF4_CFG_DDR_DIS_DLL	(0x0 << 20)
+#define EMIF4_CFG_SDR_DRV	(0x0 << 18)
+#define EMIF4_CFG_NARROW_MD	(0x0 << 14)
+#define EMIF4_CFG_CL		(0x5 << 10)
+#define EMIF4_CFG_ROWSIZE	(0x0 << 7)
+#define EMIF4_CFG_IBANK		(0x3 << 4)
+#define EMIF4_CFG_EBANK		(0x0 << 3)
+#define EMIF4_CFG_PGSIZE	(0x2)
+
+/*
+ * EMIF4 PHY Control 1 register configuration
+ */
+#define EMIF4_DDR1_EXT_STRB_EN	(0x1 << 7)
+#define EMIF4_DDR1_EXT_STRB_DIS	(0x0 << 7)
+#define EMIF4_DDR1_PWRDN_DIS	(0x0 << 6)
+#define EMIF4_DDR1_PWRDN_EN	(0x1 << 6)
+#define EMIF4_DDR1_READ_LAT	(0x6 << 0)
+
+#endif /* endif _EMIF_H_ */
diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
index 9439758..a78cf9f 100644
--- a/arch/arm/include/asm/arch-omap3/mem.h
+++ b/arch/arm/include/asm/arch-omap3/mem.h
@@ -270,4 +270,17 @@ enum {
 #define PISMO1_ONEN_BASE	ONENAND_MAP
 #define DBG_MPDB_BASE		DEBUG_BASE
 
+#ifndef __ASSEMBLY__
+
+/* Function prototypes */
+void mem_init(void);
+
+u32 is_mem_sdr(void);
+u32 mem_ok(u32 cs);
+
+u32 get_sdr_cs_size(u32);
+u32 get_sdr_cs_offset(u32);
+
+#endif	/* __ASSEMBLY__ */
+
 #endif /* endif _MEM_H_ */
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 34bd515..db7b42a 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -33,6 +33,7 @@ void per_clocks_enable(void);
 void memif_init(void);
 void sdrc_init(void);
 void do_sdrc_init(u32, u32);
+void emif4_init(void);
 void gpmc_init(void);
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
 			u32 size);
@@ -46,8 +47,6 @@ u32 get_sysboot_value(void);
 u32 is_gpmc_muxed(void);
 u32 get_gpmc0_type(void);
 u32 get_gpmc0_width(void);
-u32 get_sdr_cs_size(u32);
-u32 get_sdr_cs_offset(u32);
 u32 is_running_in_sdram(void);
 u32 is_running_in_sram(void);
 u32 is_running_in_flash(void);
diff --git a/arch/arm/include/asm/arch-orion5x/cpu.h b/arch/arm/include/asm/arch-orion5x/cpu.h
new file mode 100644
index 0000000..22e2dd3
--- /dev/null
+++ b/arch/arm/include/asm/arch-orion5x/cpu.h
@@ -0,0 +1,203 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * Based on original Kirorion5x_ood support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ORION5X_CPU_H
+#define _ORION5X_CPU_H
+
+#include <asm/system.h>
+
+#ifndef __ASSEMBLY__
+
+#define ORION5X_CPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
+			| (attr << 8) | (orion5x_winctrl_calcsize(size) << 16))
+
+#define ORION5XGBE_PORT_SERIAL_CONTROL1_REG(_x)	\
+		((_x ? ORION5X_EGIGA0_BASE : ORION5X_EGIGA1_BASE) + 0x44c)
+
+enum memory_bank {
+	BANK0,
+	BANK1,
+	BANK2,
+	BANK3
+};
+
+enum orion5x_cpu_winen {
+	ORION5X_WIN_DISABLE,
+	ORION5X_WIN_ENABLE
+};
+
+enum orion5x_cpu_target {
+	ORION5X_TARGET_DRAM = 0,
+	ORION5X_TARGET_DEVICE = 1,
+	ORION5X_TARGET_PCI = 3,
+	ORION5X_TARGET_PCIE = 4,
+	ORION5X_TARGET_SASRAM = 9
+};
+
+enum orion5x_cpu_attrib {
+	ORION5X_ATTR_DRAM_CS0 = 0x0e,
+	ORION5X_ATTR_DRAM_CS1 = 0x0d,
+	ORION5X_ATTR_DRAM_CS2 = 0x0b,
+	ORION5X_ATTR_DRAM_CS3 = 0x07,
+	ORION5X_ATTR_PCI_MEM = 0x59,
+	ORION5X_ATTR_PCI_IO = 0x51,
+	ORION5X_ATTR_PCIE_MEM = 0x59,
+	ORION5X_ATTR_PCIE_IO = 0x51,
+	ORION5X_ATTR_SASRAM = 0x00,
+	ORION5X_ATTR_DEV_CS0 = 0x1e,
+	ORION5X_ATTR_DEV_CS1 = 0x1d,
+	ORION5X_ATTR_DEV_CS2 = 0x1b,
+	ORION5X_ATTR_BOOTROM = 0x0f
+};
+
+/*
+ * Default Device Address MAP BAR values
+ */
+#define ORION5X_DEFADR_PCIE_MEM	0x90000000
+#define ORION5X_DEFADR_PCIE_MEM_REMAP_LO	0x90000000
+#define ORION5X_DEFADR_PCIE_MEM_REMAP_HI	0
+#define ORION5X_DEFSZ_PCIE_MEM	(128*1024*1024)
+
+#define ORION5X_DEFADR_PCIE_IO	0xf0000000
+#define ORION5X_DEFADR_PCIE_IO_REMAP_LO	0x90000000
+#define ORION5X_DEFADR_PCIE_IO_REMAP_HI	0
+#define ORION5X_DEFSZ_PCIE_IO	(64*1024)
+
+#define ORION5X_DEFADR_PCI_MEM	0x98000000
+#define ORION5X_DEFSZ_PCI_MEM	(128*1024*1024)
+
+#define ORION5X_DEFADR_PCI_IO	0xf0100000
+#define ORION5X_DEFSZ_PCI_IO	(64*1024)
+
+#define ORION5X_DEFADR_DEV_CS0	0xfa000000
+#define ORION5X_DEFSZ_DEV_CS0	(2*1024*1024)
+
+#define ORION5X_DEFADR_DEV_CS1	0xf8000000
+#define ORION5X_DEFSZ_DEV_CS1	(32*1024*1024)
+
+#define ORION5X_DEFADR_DEV_CS2	0xfa800000
+#define ORION5X_DEFSZ_DEV_CS2	(1*1024*1024)
+
+#define ORION5X_DEFADR_BOOTROM	0xFFF80000
+#define ORION5X_DEFSZ_BOOTROM	(512*1024)
+
+/*
+ * PCIE registers are used for SoC device ID and revision
+ */
+#define PCIE_DEV_ID_OFF         (ORION5X_REG_PCIE_BASE + 0x0000)
+#define PCIE_DEV_REV_OFF        (ORION5X_REG_PCIE_BASE + 0x0008)
+
+/*
+ * The following definitions are intended for identifying
+ * the real device and revision on which u-boot is running
+ * even if it was compiled only for a specific one. Thus,
+ * these constants must not be considered chip-specific.
+ */
+
+/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
+#define MV88F5181_DEV_ID        0x5181
+#define MV88F5181_REV_B1        3
+#define MV88F5181L_REV_A0       8
+#define MV88F5181L_REV_A1       9
+/* Orion-NAS (88F5182) */
+#define MV88F5182_DEV_ID        0x5182
+#define MV88F5182_REV_A2        2
+/* Orion-2 (88F5281) */
+#define MV88F5281_DEV_ID        0x5281
+#define MV88F5281_REV_D0        4
+#define MV88F5281_REV_D1        5
+#define MV88F5281_REV_D2        6
+/* Orion-1-90 (88F6183) */
+#define MV88F6183_DEV_ID        0x6183
+#define MV88F6183_REV_B0        3
+
+/*
+ * read feroceon core extra feature register
+ * using co-proc instruction
+ */
+static inline unsigned int readfr_extra_feature_reg(void)
+{
+	unsigned int val;
+	asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr" : "=r"
+			(val) : : "cc");
+	return val;
+}
+
+/*
+ * write feroceon core extra feature register
+ * using co-proc instruction
+ */
+static inline void writefr_extra_feature_reg(unsigned int val)
+{
+	asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr" : : "r"
+			(val) : "cc");
+	isb();
+}
+
+/*
+ * AHB to Mbus Bridge Registers
+ * Source: 88F5182 User Manual, Appendix A, section A.4
+ * Note: only windows 0 and 1 have remap capability.
+ */
+struct orion5x_win_registers {
+	u32 ctrl;
+	u32 base;
+	u32 remap_lo;
+	u32 remap_hi;
+};
+
+/*
+ * CPU control and status Registers
+ * Source: 88F5182 User Manual, Appendix A, section A.4
+ */
+struct orion5x_cpu_registers {
+	u32 config;	/*0x20100 */
+	u32 ctrl_stat;	/*0x20104 */
+	u32 rstoutn_mask; /* 0x20108 */
+	u32 sys_soft_rst; /* 0x2010C */
+	u32 ahb_mbus_cause_irq; /* 0x20110 */
+	u32 ahb_mbus_mask_irq; /* 0x20114 */
+};
+
+/*
+ * DDR SDRAM Controller Address Decode Registers
+ * Source: 88F5182 User Manual, Appendix A, section A.5.1
+ */
+struct orion5x_ddr_addr_decode_registers {
+	u32 base;
+	u32 size;
+};
+
+/*
+ * functions
+ */
+void reset_cpu(unsigned long ignored);
+u32 orion5x_device_id(void);
+u32 orion5x_device_rev(void);
+unsigned int orion5x_winctrl_calcsize(unsigned int sizeval);
+#endif /* __ASSEMBLY__ */
+#endif /* _ORION5X_CPU_H */
diff --git a/arch/arm/include/asm/arch-orion5x/mv88f5182.h b/arch/arm/include/asm/arch-orion5x/mv88f5182.h
new file mode 100644
index 0000000..86ba08d
--- /dev/null
+++ b/arch/arm/include/asm/arch-orion5x/mv88f5182.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * Based on original Kirkwood 88F6182 support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * Header file for Feroceon CPU core 88F5182 SOC.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_88F5182_H
+#define _CONFIG_88F5182_H
+
+/* SOC specific definitions */
+#define F88F5182_REGS_PHYS_BASE		0xf1000000
+#define ORION5X_REGS_PHY_BASE		F88F5182_REGS_PHYS_BASE
+
+/* TCLK Core Clock defination */
+#define CONFIG_SYS_TCLK			166000000 /* 166MHz */
+
+#endif /* _CONFIG_88F5182_H */
diff --git a/arch/arm/include/asm/arch-orion5x/orion5x.h b/arch/arm/include/asm/arch-orion5x/orion5x.h
new file mode 100644
index 0000000..4008c84
--- /dev/null
+++ b/arch/arm/include/asm/arch-orion5x/orion5x.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * Based on original Kirkwood support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * Header file for Marvell's Orion SoC with Feroceon CPU core.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ASM_ARCH_ORION5X_H
+#define _ASM_ARCH_ORION5X_H
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <asm/io.h>
+#endif /* __ASSEMBLY__ */
+
+#if defined(CONFIG_FEROCEON)
+#include <asm/arch/cpu.h>
+
+/* SOC specific definations */
+#define ORION5X_REGISTER(x)			(ORION5X_REGS_PHY_BASE + x)
+
+/* Documented registers */
+#define ORION5X_TWSI_BASE			(ORION5X_REGISTER(0x11000))
+#define ORION5X_UART0_BASE			(ORION5X_REGISTER(0x12000))
+#define ORION5X_UART1_BASE			(ORION5X_REGISTER(0x12100))
+#define ORION5X_MPP_BASE			(ORION5X_REGISTER(0x10000))
+#define ORION5X_GPIO_BASE			(ORION5X_REGISTER(0x10100))
+#define ORION5X_CPU_WIN_BASE			(ORION5X_REGISTER(0x20000))
+#define ORION5X_CPU_REG_BASE			(ORION5X_REGISTER(0x20100))
+#define ORION5X_TIMER_BASE			(ORION5X_REGISTER(0x20300))
+#define ORION5X_REG_PCI_BASE			(ORION5X_REGISTER(0x30000))
+#define ORION5X_REG_PCIE_BASE			(ORION5X_REGISTER(0x40000))
+#define ORION5X_USB20_PORT0_BASE		(ORION5X_REGISTER(0x50000))
+#define ORION5X_USB20_PORT1_BASE		(ORION5X_REGISTER(0xA0000))
+#define ORION5X_EGIGA_BASE			(ORION5X_REGISTER(0x72000))
+
+#define CONFIG_MAX_RAM_BANK_SIZE		(64*1024*1024)
+
+/* include here SoC variants. 5181, 5281, 6183 should go here when
+   adding support for them, and this comment should then be updated. */
+#if defined(CONFIG_88F5182)
+#include <asm/arch/mv88f5182.h>
+#else
+#error "SOC Name not defined"
+#endif
+#endif /* CONFIG_FEROCEON */
+#endif /* _ASM_ARCH_ORION5X_H */
diff --git a/arch/arm/include/asm/arch-tnetv107x/clock.h b/arch/arm/include/asm/arch-tnetv107x/clock.h
new file mode 100644
index 0000000..097f825
--- /dev/null
+++ b/arch/arm/include/asm/arch-tnetv107x/clock.h
@@ -0,0 +1,68 @@
+/*
+ * TNETV107X: Clock APIs
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#define PSC_MDCTL_NEXT_SWRSTDISABLE	0x0
+#define PSC_MDCTL_NEXT_SYNCRST		0x1
+#define PSC_MDCTL_NEXT_DISABLE		0x2
+#define PSC_MDCTL_NEXT_ENABLE		0x3
+
+#define CONFIG_SYS_INT_OSC_FREQ		24000000
+
+#ifndef __ASSEMBLY__
+
+/* PLL identifiers */
+enum pll_type_e {
+	SYS_PLL,
+	TDM_PLL,
+	ETH_PLL
+};
+
+/* PLL configuration data */
+struct pll_init_data {
+	int pll;
+	int internal_osc;
+	unsigned long pll_freq;
+	unsigned long div_freq[10];
+};
+
+void init_plls(int num_pll, struct pll_init_data *config);
+int  lpsc_status(unsigned int mod);
+void lpsc_control(int mod, unsigned long state, int lrstz);
+unsigned long clk_get_rate(unsigned int clk);
+unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
+int clk_set_rate(unsigned int clk, unsigned long hz);
+
+static inline void clk_enable(unsigned int mod)
+{
+	lpsc_control(mod, PSC_MDCTL_NEXT_ENABLE, -1);
+}
+
+static inline void clk_disable(unsigned int mod)
+{
+	lpsc_control(mod, PSC_MDCTL_NEXT_DISABLE, -1);
+}
+
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-tnetv107x/emif_defs.h b/arch/arm/include/asm/arch-tnetv107x/emif_defs.h
new file mode 100644
index 0000000..9969a01
--- /dev/null
+++ b/arch/arm/include/asm/arch-tnetv107x/emif_defs.h
@@ -0,0 +1 @@
+#include <asm/arch-davinci/emif_defs.h>
diff --git a/arch/arm/include/asm/arch-tnetv107x/hardware.h b/arch/arm/include/asm/arch-tnetv107x/hardware.h
new file mode 100644
index 0000000..94a94f9
--- /dev/null
+++ b/arch/arm/include/asm/arch-tnetv107x/hardware.h
@@ -0,0 +1,173 @@
+/*
+ * TNETV107X: Hardware information
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#ifndef __ASSEMBLY__
+
+#include <asm/sizes.h>
+
+#define ASYNC_EMIF_NUM_CS		4
+#define ASYNC_EMIF_MODE_NOR		0
+#define ASYNC_EMIF_MODE_NAND		1
+#define ASYNC_EMIF_MODE_ONENAND		2
+#define ASYNC_EMIF_PRESERVE		-1
+
+struct async_emif_config {
+	unsigned mode;
+	unsigned select_strobe;
+	unsigned extend_wait;
+	unsigned wr_setup;
+	unsigned wr_strobe;
+	unsigned wr_hold;
+	unsigned rd_setup;
+	unsigned rd_strobe;
+	unsigned rd_hold;
+	unsigned turn_around;
+	enum {
+		ASYNC_EMIF_8	= 0,
+		ASYNC_EMIF_16	= 1,
+		ASYNC_EMIF_32	= 2,
+	} width;
+};
+
+void init_async_emif(int num_cs, struct async_emif_config *config);
+
+int wdt_start(unsigned long msecs);
+int wdt_stop(void);
+int wdt_kick(void);
+
+#endif
+
+/* Chip configuration unlock codes and registers */
+#define TNETV107X_KICK0		(TNETV107X_CHIP_CONFIG_SYS_BASE+0x38)
+#define TNETV107X_KICK1		(TNETV107X_CHIP_CONFIG_SYS_BASE+0x3c)
+#define TNETV107X_PINMUX(n)	(TNETV107X_CHIP_CONFIG_SYS_BASE+0x150+(n)*4)
+#define TNETV107X_KICK0_MAGIC	0x83e70b13
+#define TNETV107X_KICK1_MAGIC	0x95a4f1e0
+
+/* Module base addresses */
+#define TNETV107X_TPCC_BASE			0x01C00000
+#define TNETV107X_TPTC0_BASE			0x01C10000
+#define TNETV107X_TPTC1_BASE			0x01C10400
+#define TNETV107X_INTC_BASE			0x03000000
+#define TNETV107X_LCD_CONTROLLER_BASE		0x08030000
+#define TNETV107X_INTD_BASE			0x08038000
+#define TNETV107X_INTD_IPC_BASE			0x08038000
+#define TNETV107X_INTD_FAST_BASE		0x08039000
+#define TNETV107X_INTD_ASYNC_BASE		0x0803A000
+#define TNETV107X_INTD_SLOW_BASE		0x0803B000
+#define TNETV107X_PKA_BASE			0x08040000
+#define TNETV107X_RNG_BASE			0x08044000
+#define TNETV107X_TIMER0_BASE			0x08086500
+#define TNETV107X_TIMER1_BASE			0x08086600
+#define TNETV107X_WDT0_ARM_BASE			0x08086700
+#define TNETV107X_WDT1_DSP_BASE			0x08086800
+#define TNETV107X_CHIP_CONFIG_SYS_BASE		0x08087000
+#define TNETV107X_GPIO_BASE			0x08088000
+#define TNETV107X_UART1_BASE			0x08088400
+#define TNETV107X_TOUCHSCREEN_BASE		0x08088500
+#define TNETV107X_SDIO0_BASE			0x08088700
+#define TNETV107X_SDIO1_BASE			0x08088800
+#define TNETV107X_MDIO_BASE			0x08088900
+#define TNETV107X_KEYPAD_BASE			0x08088A00
+#define TNETV107X_SSP_BASE			0x08088C00
+#define TNETV107X_CLOCK_CONTROL_BASE		0x0808A000
+#define TNETV107X_PSC_BASE			0x0808B000
+#define TNETV107X_TDM0_BASE			0x08100000
+#define TNETV107X_TDM1_BASE			0x08100100
+#define TNETV107X_MCDMA_BASE			0x08108000
+#define TNETV107X_UART0_DMA_BASE		0x08108200
+#define TNETV107X_USBSS_BASE			0x08120000
+#define TNETV107X_VLYNQ_CONTROL_BASE		0x0810D000
+#define TNETV107X_ASYNC_EMIF_CNTRL_BASE		0x08200000
+#define TNETV107X_VLYNQ_MEM_MAP_BASE		0x0C000000
+#define TNETV107X_IMCOP_BASE			0x01CC0000
+#define TNETV107X_MBX_LITE_BASE			0x07000000
+#define TNETV107X_ETHSS_BASE			0x0803C000
+#define TNETV107X_CPSW_BASE			0x0803C000
+#define TNETV107X_SPF_BASE			0x0803C800
+#define TNETV107X_IOPU_ETHSS_BASE		0x0803D000
+#define TNETV107X_VTP_CNTRL_0			0x0803D800
+#define TNETV107X_VTP_CNTRL_1			0x0803D900
+#define TNETV107X_UART2_DMA_BASE		0x08108400
+#define TNETV107X_INTERNAL_MEMORY		0x20000000
+#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE	0x30000000
+#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE	0x40000000
+#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE	0x44000000
+#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE	0x48000000
+#define TNETV107X_DDR_EMIF_DATA_BASE		0x80000000
+#define TNETV107X_DDR_EMIF_CONTROL_BASE		0x90000000
+
+/* LPSC module definitions */
+#define TNETV107X_LPSC_ARM			0
+#define TNETV107X_LPSC_GEM			1
+#define TNETV107X_LPSC_DDR2_PHY			2
+#define TNETV107X_LPSC_TPCC			3
+#define TNETV107X_LPSC_TPTC0			4
+#define TNETV107X_LPSC_TPTC1			5
+#define TNETV107X_LPSC_RAM			6
+#define TNETV107X_LPSC_MBX_LITE			7
+#define TNETV107X_LPSC_LCD			8
+#define TNETV107X_LPSC_ETHSS			9
+#define TNETV107X_LPSC_AEMIF			10
+#define TNETV107X_LPSC_CHIP_CFG			11
+#define TNETV107X_LPSC_TSC			12
+#define TNETV107X_LPSC_ROM			13
+#define TNETV107X_LPSC_UART2			14
+#define TNETV107X_LPSC_PKTSEC			15
+#define TNETV107X_LPSC_SECCTL			16
+#define TNETV107X_LPSC_KEYMGR			17
+#define TNETV107X_LPSC_KEYPAD			18
+#define TNETV107X_LPSC_GPIO			19
+#define TNETV107X_LPSC_MDIO			20
+#define TNETV107X_LPSC_SDIO0			21
+#define TNETV107X_LPSC_UART0			22
+#define TNETV107X_LPSC_UART1			23
+#define TNETV107X_LPSC_TIMER0			24
+#define TNETV107X_LPSC_TIMER1			25
+#define TNETV107X_LPSC_WDT_ARM			26
+#define TNETV107X_LPSC_WDT_DSP			27
+#define TNETV107X_LPSC_SSP			28
+#define TNETV107X_LPSC_TDM0			29
+#define TNETV107X_LPSC_VLYNQ			30
+#define TNETV107X_LPSC_MCDMA			31
+#define TNETV107X_LPSC_USB0			32
+#define TNETV107X_LPSC_TDM1			33
+#define TNETV107X_LPSC_DEBUGSS			34
+#define TNETV107X_LPSC_ETHSS_RGMII		35
+#define TNETV107X_LPSC_SYSTEM			36
+#define TNETV107X_LPSC_IMCOP			37
+#define TNETV107X_LPSC_SPARE			38
+#define TNETV107X_LPSC_SDIO1			39
+#define TNETV107X_LPSC_USB1			40
+#define TNETV107X_LPSC_USBSS			41
+#define TNETV107X_LPSC_DDR2_EMIF1_VRST		42
+#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST	43
+#define TNETV107X_LPSC_MAX			44
+
+/* Interrupt controller */
+#define INTC_GLB_EN			(TNETV107X_INTC_BASE + 0x10)
+#define INTC_HINT_EN			(TNETV107X_INTC_BASE + 0x1500)
+#define INTC_EN_CLR0			(TNETV107X_INTC_BASE + 0x380)
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-tnetv107x/mux.h b/arch/arm/include/asm/arch-tnetv107x/mux.h
new file mode 100644
index 0000000..f16bc99
--- /dev/null
+++ b/arch/arm/include/asm/arch-tnetv107x/mux.h
@@ -0,0 +1,306 @@
+/*
+ * TNETV107X: Pinmux APIs
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_MUX_H
+#define __ASM_ARCH_MUX_H
+
+struct pin_config {
+	unsigned char reg_index;
+	unsigned char mask_offset;
+	unsigned char mode;
+};
+
+#define TNETV107X_MUX_CFG(reg, offset, mux_mode) \
+			{ reg, offset, mux_mode }
+
+int mux_select_pin(short index);
+int mux_select_pins(const short *pins);
+
+enum tnetv107x_pin_mux_index {
+	TNETV107X_PIN_ASR_A00,
+	TNETV107X_PIN_GPIO32,
+	TNETV107X_PIN_ASR_A01,
+	TNETV107X_PIN_GPIO33,
+	TNETV107X_PIN_ASR_A02,
+	TNETV107X_PIN_GPIO34,
+	TNETV107X_PIN_ASR_A03,
+	TNETV107X_PIN_GPIO35,
+	TNETV107X_PIN_ASR_A04,
+	TNETV107X_PIN_GPIO36,
+	TNETV107X_PIN_ASR_A05,
+	TNETV107X_PIN_GPIO37,
+	TNETV107X_PIN_ASR_A06,
+	TNETV107X_PIN_GPIO38,
+	TNETV107X_PIN_ASR_A07,
+	TNETV107X_PIN_GPIO39,
+	TNETV107X_PIN_ASR_A08,
+	TNETV107X_PIN_GPIO40,
+	TNETV107X_PIN_ASR_A09,
+	TNETV107X_PIN_GPIO41,
+	TNETV107X_PIN_ASR_A10,
+	TNETV107X_PIN_GPIO42,
+	TNETV107X_PIN_ASR_A11,
+	TNETV107X_PIN_BOOT_STRP_0,
+	TNETV107X_PIN_ASR_A12,
+	TNETV107X_PIN_BOOT_STRP_1,
+	TNETV107X_PIN_ASR_A13,
+	TNETV107X_PIN_GPIO43,
+	TNETV107X_PIN_ASR_A14,
+	TNETV107X_PIN_GPIO44,
+	TNETV107X_PIN_ASR_A15,
+	TNETV107X_PIN_GPIO45,
+	TNETV107X_PIN_ASR_A16,
+	TNETV107X_PIN_GPIO46,
+	TNETV107X_PIN_ASR_A17,
+	TNETV107X_PIN_GPIO47,
+	TNETV107X_PIN_ASR_A18,
+	TNETV107X_PIN_GPIO48,
+	TNETV107X_PIN_SDIO1_DATA3_0,
+	TNETV107X_PIN_ASR_A19,
+	TNETV107X_PIN_GPIO49,
+	TNETV107X_PIN_SDIO1_DATA2_0,
+	TNETV107X_PIN_ASR_A20,
+	TNETV107X_PIN_GPIO50,
+	TNETV107X_PIN_SDIO1_DATA1_0,
+	TNETV107X_PIN_ASR_A21,
+	TNETV107X_PIN_GPIO51,
+	TNETV107X_PIN_SDIO1_DATA0_0,
+	TNETV107X_PIN_ASR_A22,
+	TNETV107X_PIN_GPIO52,
+	TNETV107X_PIN_SDIO1_CMD_0,
+	TNETV107X_PIN_ASR_A23,
+	TNETV107X_PIN_GPIO53,
+	TNETV107X_PIN_SDIO1_CLK_0,
+	TNETV107X_PIN_ASR_BA_1,
+	TNETV107X_PIN_GPIO54,
+	TNETV107X_PIN_SYS_PLL_CLK,
+	TNETV107X_PIN_ASR_CS0,
+	TNETV107X_PIN_ASR_CS1,
+	TNETV107X_PIN_ASR_CS2,
+	TNETV107X_PIN_TDM_PLL_CLK,
+	TNETV107X_PIN_ASR_CS3,
+	TNETV107X_PIN_ETH_PHY_CLK,
+	TNETV107X_PIN_ASR_D00,
+	TNETV107X_PIN_GPIO55,
+	TNETV107X_PIN_ASR_D01,
+	TNETV107X_PIN_GPIO56,
+	TNETV107X_PIN_ASR_D02,
+	TNETV107X_PIN_GPIO57,
+	TNETV107X_PIN_ASR_D03,
+	TNETV107X_PIN_GPIO58,
+	TNETV107X_PIN_ASR_D04,
+	TNETV107X_PIN_GPIO59_0,
+	TNETV107X_PIN_ASR_D05,
+	TNETV107X_PIN_GPIO60_0,
+	TNETV107X_PIN_ASR_D06,
+	TNETV107X_PIN_GPIO61_0,
+	TNETV107X_PIN_ASR_D07,
+	TNETV107X_PIN_GPIO62_0,
+	TNETV107X_PIN_ASR_D08,
+	TNETV107X_PIN_GPIO63_0,
+	TNETV107X_PIN_ASR_D09,
+	TNETV107X_PIN_GPIO64_0,
+	TNETV107X_PIN_ASR_D10,
+	TNETV107X_PIN_SDIO1_DATA3_1,
+	TNETV107X_PIN_ASR_D11,
+	TNETV107X_PIN_SDIO1_DATA2_1,
+	TNETV107X_PIN_ASR_D12,
+	TNETV107X_PIN_SDIO1_DATA1_1,
+	TNETV107X_PIN_ASR_D13,
+	TNETV107X_PIN_SDIO1_DATA0_1,
+	TNETV107X_PIN_ASR_D14,
+	TNETV107X_PIN_SDIO1_CMD_1,
+	TNETV107X_PIN_ASR_D15,
+	TNETV107X_PIN_SDIO1_CLK_1,
+	TNETV107X_PIN_ASR_OE,
+	TNETV107X_PIN_BOOT_STRP_2,
+	TNETV107X_PIN_ASR_RNW,
+	TNETV107X_PIN_GPIO29_0,
+	TNETV107X_PIN_ASR_WAIT,
+	TNETV107X_PIN_GPIO30_0,
+	TNETV107X_PIN_ASR_WE,
+	TNETV107X_PIN_BOOT_STRP_3,
+	TNETV107X_PIN_ASR_WE_DQM0,
+	TNETV107X_PIN_GPIO31,
+	TNETV107X_PIN_LCD_PD17_0,
+	TNETV107X_PIN_ASR_WE_DQM1,
+	TNETV107X_PIN_ASR_BA0_0,
+	TNETV107X_PIN_VLYNQ_CLK,
+	TNETV107X_PIN_GPIO14,
+	TNETV107X_PIN_LCD_PD19_0,
+	TNETV107X_PIN_VLYNQ_RXD0,
+	TNETV107X_PIN_GPIO15,
+	TNETV107X_PIN_LCD_PD20_0,
+	TNETV107X_PIN_VLYNQ_RXD1,
+	TNETV107X_PIN_GPIO16,
+	TNETV107X_PIN_LCD_PD21_0,
+	TNETV107X_PIN_VLYNQ_TXD0,
+	TNETV107X_PIN_GPIO17,
+	TNETV107X_PIN_LCD_PD22_0,
+	TNETV107X_PIN_VLYNQ_TXD1,
+	TNETV107X_PIN_GPIO18,
+	TNETV107X_PIN_LCD_PD23_0,
+	TNETV107X_PIN_SDIO0_CLK,
+	TNETV107X_PIN_GPIO19,
+	TNETV107X_PIN_SDIO0_CMD,
+	TNETV107X_PIN_GPIO20,
+	TNETV107X_PIN_SDIO0_DATA0,
+	TNETV107X_PIN_GPIO21,
+	TNETV107X_PIN_SDIO0_DATA1,
+	TNETV107X_PIN_GPIO22,
+	TNETV107X_PIN_SDIO0_DATA2,
+	TNETV107X_PIN_GPIO23,
+	TNETV107X_PIN_SDIO0_DATA3,
+	TNETV107X_PIN_GPIO24,
+	TNETV107X_PIN_EMU0,
+	TNETV107X_PIN_EMU1,
+	TNETV107X_PIN_RTCK,
+	TNETV107X_PIN_TRST_N,
+	TNETV107X_PIN_TCK,
+	TNETV107X_PIN_TDI,
+	TNETV107X_PIN_TDO,
+	TNETV107X_PIN_TMS,
+	TNETV107X_PIN_TDM1_CLK,
+	TNETV107X_PIN_TDM1_RX,
+	TNETV107X_PIN_TDM1_TX,
+	TNETV107X_PIN_TDM1_FS,
+	TNETV107X_PIN_KEYPAD_R0,
+	TNETV107X_PIN_KEYPAD_R1,
+	TNETV107X_PIN_KEYPAD_R2,
+	TNETV107X_PIN_KEYPAD_R3,
+	TNETV107X_PIN_KEYPAD_R4,
+	TNETV107X_PIN_KEYPAD_R5,
+	TNETV107X_PIN_KEYPAD_R6,
+	TNETV107X_PIN_GPIO12,
+	TNETV107X_PIN_KEYPAD_R7,
+	TNETV107X_PIN_GPIO10,
+	TNETV107X_PIN_KEYPAD_C0,
+	TNETV107X_PIN_KEYPAD_C1,
+	TNETV107X_PIN_KEYPAD_C2,
+	TNETV107X_PIN_KEYPAD_C3,
+	TNETV107X_PIN_KEYPAD_C4,
+	TNETV107X_PIN_KEYPAD_C5,
+	TNETV107X_PIN_KEYPAD_C6,
+	TNETV107X_PIN_GPIO13,
+	TNETV107X_PIN_TEST_CLK_IN,
+	TNETV107X_PIN_KEYPAD_C7,
+	TNETV107X_PIN_GPIO11,
+	TNETV107X_PIN_SSP0_0,
+	TNETV107X_PIN_SCC_DCLK,
+	TNETV107X_PIN_LCD_PD20_1,
+	TNETV107X_PIN_SSP0_1,
+	TNETV107X_PIN_SCC_CS_N,
+	TNETV107X_PIN_LCD_PD21_1,
+	TNETV107X_PIN_SSP0_2,
+	TNETV107X_PIN_SCC_D,
+	TNETV107X_PIN_LCD_PD22_1,
+	TNETV107X_PIN_SSP0_3,
+	TNETV107X_PIN_SCC_RESETN,
+	TNETV107X_PIN_LCD_PD23_1,
+	TNETV107X_PIN_SSP1_0,
+	TNETV107X_PIN_GPIO25,
+	TNETV107X_PIN_UART2_CTS,
+	TNETV107X_PIN_SSP1_1,
+	TNETV107X_PIN_GPIO26,
+	TNETV107X_PIN_UART2_RD,
+	TNETV107X_PIN_SSP1_2,
+	TNETV107X_PIN_GPIO27,
+	TNETV107X_PIN_UART2_RTS,
+	TNETV107X_PIN_SSP1_3,
+	TNETV107X_PIN_GPIO28,
+	TNETV107X_PIN_UART2_TD,
+	TNETV107X_PIN_UART0_CTS,
+	TNETV107X_PIN_UART0_RD,
+	TNETV107X_PIN_UART0_RTS,
+	TNETV107X_PIN_UART0_TD,
+	TNETV107X_PIN_UART1_RD,
+	TNETV107X_PIN_UART1_TD,
+	TNETV107X_PIN_LCD_AC_NCS,
+	TNETV107X_PIN_LCD_HSYNC_RNW,
+	TNETV107X_PIN_LCD_VSYNC_A0,
+	TNETV107X_PIN_LCD_MCLK,
+	TNETV107X_PIN_LCD_PD16_0,
+	TNETV107X_PIN_LCD_PCLK_E,
+	TNETV107X_PIN_LCD_PD00,
+	TNETV107X_PIN_LCD_PD01,
+	TNETV107X_PIN_LCD_PD02,
+	TNETV107X_PIN_LCD_PD03,
+	TNETV107X_PIN_LCD_PD04,
+	TNETV107X_PIN_LCD_PD05,
+	TNETV107X_PIN_LCD_PD06,
+	TNETV107X_PIN_LCD_PD07,
+	TNETV107X_PIN_LCD_PD08,
+	TNETV107X_PIN_GPIO59_1,
+	TNETV107X_PIN_LCD_PD09,
+	TNETV107X_PIN_GPIO60_1,
+	TNETV107X_PIN_LCD_PD10,
+	TNETV107X_PIN_ASR_BA0_1,
+	TNETV107X_PIN_GPIO61_1,
+	TNETV107X_PIN_LCD_PD11,
+	TNETV107X_PIN_GPIO62_1,
+	TNETV107X_PIN_LCD_PD12,
+	TNETV107X_PIN_GPIO63_1,
+	TNETV107X_PIN_LCD_PD13,
+	TNETV107X_PIN_GPIO64_1,
+	TNETV107X_PIN_LCD_PD14,
+	TNETV107X_PIN_GPIO29_1,
+	TNETV107X_PIN_LCD_PD15,
+	TNETV107X_PIN_GPIO30_1,
+	TNETV107X_PIN_EINT0,
+	TNETV107X_PIN_GPIO08,
+	TNETV107X_PIN_EINT1,
+	TNETV107X_PIN_GPIO09,
+	TNETV107X_PIN_GPIO00,
+	TNETV107X_PIN_LCD_PD20_2,
+	TNETV107X_PIN_TDM_CLK_IN_2,
+	TNETV107X_PIN_GPIO01,
+	TNETV107X_PIN_LCD_PD21_2,
+	TNETV107X_PIN_24M_CLK_OUT_1,
+	TNETV107X_PIN_GPIO02,
+	TNETV107X_PIN_LCD_PD22_2,
+	TNETV107X_PIN_GPIO03,
+	TNETV107X_PIN_LCD_PD23_2,
+	TNETV107X_PIN_GPIO04,
+	TNETV107X_PIN_LCD_PD16_1,
+	TNETV107X_PIN_USB0_RXERR,
+	TNETV107X_PIN_GPIO05,
+	TNETV107X_PIN_LCD_PD17_1,
+	TNETV107X_PIN_TDM_CLK_IN_1,
+	TNETV107X_PIN_GPIO06,
+	TNETV107X_PIN_LCD_PD18,
+	TNETV107X_PIN_24M_CLK_OUT_2,
+	TNETV107X_PIN_GPIO07,
+	TNETV107X_PIN_LCD_PD19_1,
+	TNETV107X_PIN_USB1_RXERR,
+	TNETV107X_PIN_ETH_PLL_CLK,
+	TNETV107X_PIN_MDIO,
+	TNETV107X_PIN_MDC,
+	TNETV107X_PIN_AIC_MUTE_STAT_N,
+	TNETV107X_PIN_TDM0_CLK,
+	TNETV107X_PIN_AIC_HNS_EN_N,
+	TNETV107X_PIN_TDM0_FS,
+	TNETV107X_PIN_AIC_HDS_EN_STAT_N,
+	TNETV107X_PIN_TDM0_TX,
+	TNETV107X_PIN_AIC_HNF_EN_STAT_N,
+	TNETV107X_PIN_TDM0_RX,
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-tnetv107x/nand_defs.h b/arch/arm/include/asm/arch-tnetv107x/nand_defs.h
new file mode 100644
index 0000000..961b710
--- /dev/null
+++ b/arch/arm/include/asm/arch-tnetv107x/nand_defs.h
@@ -0,0 +1,38 @@
+/*
+ * TNETV107X: NAND definitions
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef _NAND_DEFS_H_
+#define _NAND_DEFS_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/emif_defs.h>
+
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE	TNETV107X_ASYNC_EMIF_CNTRL_BASE
+
+#define	MASK_CLE		0x4000
+#define	MASK_ALE		0x2000
+
+#define NAND_READ_START		0x00
+#define NAND_READ_END		0x30
+#define NAND_STATUS		0x70
+
+extern void davinci_nand_init(struct nand_chip *nand);
+
+#endif