ENGR00315499-7 Add EPDC splash screen for MX 6DL SabreSD and 6SL EVK

Add EPDC splash screen feature for MX6SL EVK, and MX6DL SABRESD board.

- Currently, splash screen consists of a simple black border
  around a white screen.  Done this way to save in memory footprint.

- EPDC splash screen is disabled by default in the config file for MX6DL_SABRESD
  and MX6SL_EVK.  If left enabled, the U-Boot image will not boot correctly
  (hang), since some additional content on the boot device (waveform file) is
  required for EPDC splash to work correctly.

Please refer to Linux Reference Manual for how to flash WAVEFORM file.

Signed-off-by: Robby Cai <R63905@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>

2 files changed, 48 insertions, 0 deletions

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 30210f2..8124ce2 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -162,6 +162,7 @@
 #define DCIC2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
 #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
 #endif
+#define EPDC_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x74000)
 
 #define AIPS2_ON_BASE_ADDR          (ATZ2_BASE_ADDR + 0x7C000)
 #define AIPS2_OFF_BASE_ADDR         (ATZ2_BASE_ADDR + 0x80000)
@@ -436,6 +437,8 @@ struct cspi_regs {
 	ECSPI5_BASE_ADDR
 #endif
 
+#define ANATOP_PLL_VIDEO        0xA0
+
 struct ocotp_regs {
 	u32	ctrl;
 	u32	ctrl_set;
diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
index 774314d..9e68d95 100644
--- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
@@ -30,6 +30,51 @@ enum {
 	MX6_PAD_FEC_REF_CLK__FEC_REF_OUT			= IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0),
 	MX6_PAD_FEC_RX_ER__GPIO_4_19				= IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0),
 	MX6_PAD_FEC_TX_CLK__GPIO_4_21				= IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_PWRSTAT__GPIO_2_13				= IOMUX_PAD(0x03E8, 0x00F8, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_VCOM0__GPIO_2_3				= IOMUX_PAD(0x0410, 0x0120, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_PWRWAKEUP__GPIO_2_14			= IOMUX_PAD(0x03EC, 0x00FC, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_PWRCTRL0__GPIO_2_7				= IOMUX_PAD(0x03D4, 0x00E4, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D0__EPDC_SDDO_0				= IOMUX_PAD(0x0380, 0x0090, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D1__EPDC_SDDO_1				= IOMUX_PAD(0x0384, 0x0094, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D2__EPDC_SDDO_2				= IOMUX_PAD(0x03A0, 0x00B0, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D3__EPDC_SDDO_3				= IOMUX_PAD(0x03A4, 0x00B4, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D4__EPDC_SDDO_4				= IOMUX_PAD(0x03A8, 0x00B8, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D5__EPDC_SDDO_5				= IOMUX_PAD(0x03AC, 0x00BC, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D6__EPDC_SDDO_6				= IOMUX_PAD(0x03B0, 0x00C0, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D7__EPDC_SDDO_7				= IOMUX_PAD(0x03B4, 0x00C4, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_GDCLK__EPDC_GDCLK				= IOMUX_PAD(0x03C0, 0x00D0, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_GDSP__EPDC_GDSP				= IOMUX_PAD(0x03CC, 0x00DC, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_GDOE__EPDC_GDOE				= IOMUX_PAD(0x03C4, 0x00D4, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_GDRL__EPDC_GDRL				= IOMUX_PAD(0x03C8, 0x00D8, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDCLK__EPDC_SDCLK				= IOMUX_PAD(0x0400, 0x0110, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDOE__EPDC_SDOE				= IOMUX_PAD(0x0408, 0x0118, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDLE__EPDC_SDLE				= IOMUX_PAD(0x0404, 0x0114, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDSHR__EPDC_SDSHR				= IOMUX_PAD(0x040C, 0x011C, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_BDR0__EPDC_BDR_0				= IOMUX_PAD(0x0378, 0x0088, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDCE0__EPDC_SDCE_0				= IOMUX_PAD(0x03F0, 0x0100, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDCE1__EPDC_SDCE_1				= IOMUX_PAD(0x03F4, 0x0104, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDCE2__EPDC_SDCE_2				= IOMUX_PAD(0x03F8, 0x0108, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D0__GPIO_1_7				= IOMUX_PAD(0x0380, 0x0090, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D1__GPIO_1_8				= IOMUX_PAD(0x0384, 0x0094, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D2__GPIO_1_9				= IOMUX_PAD(0x03A0, 0x00B0, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D3__GPIO_1_10				= IOMUX_PAD(0x03A4, 0x00B4, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D4__GPIO_1_11				= IOMUX_PAD(0x03A8, 0x00B8, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D5__GPIO_1_12				= IOMUX_PAD(0x03AC, 0x00BC, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D6__GPIO_1_13				= IOMUX_PAD(0x03B0, 0x00C0, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D7__GPIO_1_14				= IOMUX_PAD(0x03B4, 0x00C4, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_GDCLK__GPIO_1_31				= IOMUX_PAD(0x03C0, 0x00D0, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_GDSP__GPIO_2_2				= IOMUX_PAD(0x03CC, 0x00DC, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_GDOE__GPIO_2_0				= IOMUX_PAD(0x03C4, 0x00D4, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_GDRL__GPIO_2_1				= IOMUX_PAD(0x03C8, 0x00D8, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDCLK__GPIO_1_23				= IOMUX_PAD(0x0400, 0x0110, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDOE__GPIO_1_25				= IOMUX_PAD(0x0408, 0x0118, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDLE__GPIO_1_24				= IOMUX_PAD(0x0404, 0x0114, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDSHR__GPIO_1_26				= IOMUX_PAD(0x040C, 0x011C, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_BDR0__GPIO_2_5				= IOMUX_PAD(0x0378, 0x0088, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDCE0__GPIO_1_27				= IOMUX_PAD(0x03F0, 0x0100, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDCE1__GPIO_1_28				= IOMUX_PAD(0x03F4, 0x0104, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDCE2__GPIO_1_29				= IOMUX_PAD(0x03F8, 0x0108, 5, 0x0000, 0, 0),
 	MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID      = IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, 0),
 };
 #endif	/* __ASM_ARCH_MX6_MX6SL_PINS_H__ */