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authorLokesh Vutla <lokeshvutla@ti.com>2013-02-12 01:33:45 +0000
committerTom Rini <trini@ti.com>2013-03-11 11:06:11 -0400
commitd4d986ee27fe6a78e50d4789d5b08b87a5e64892 (patch)
tree0bc6adb8e8d303a5512194a6f5cb4a426e678079 /arch/arm/include
parent9100edecf8379c357037c34044757202f85480b2 (diff)
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ARM: OMAP5: srcomp: enable slew rate compensation cells after powerup
After power-up SRCOMP cells are by-passed by default in OMAP5. Software has to enable these SRCOMP sells. For ES2: All 5 SRCOMP cells needs to be enabled. For ES1: Only 4 SRCOMP cells in core power domain are enabled. The 1 in wkup domain is not enabled because smart i/os of wkup domain work with default compensation code. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com> Cc: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/arch-omap5/clocks.h4
-rw-r--r--arch/arm/include/asm/arch-omap5/omap.h19
-rw-r--r--arch/arm/include/asm/arch-omap5/sys_proto.h1
-rw-r--r--arch/arm/include/asm/omap_common.h2
4 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h
index 6ee40be..cfde374 100644
--- a/arch/arm/include/asm/arch-omap5/clocks.h
+++ b/arch/arm/include/asm/arch-omap5/clocks.h
@@ -186,6 +186,10 @@
#define OPTFCLKEN_SCRM_CORE_SHIFT 8
#define OPTFCLKEN_SCRM_CORE_MASK (1 << 8)
+/* CM_COREAON_IO_SRCOMP_CLKCTRL */
+#define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8
+#define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8)
+
/* Clock frequencies */
#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000
#define OMAP_SYS_CLK_IND_38_4_MHZ 6
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index ba2775b..d29be93 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -229,7 +229,26 @@ struct s32ktimer {
#define CH_FLAGS_CHFLASH (0x1 << 2)
#define CH_FLAGS_CHMMCSD (0x1 << 3)
+/* CONTROL_SRCOMP_XXX_SIDE */
+#define OVERRIDE_XS_SHIFT 30
+#define OVERRIDE_XS_MASK (1 << 30)
+#define SRCODE_READ_XS_SHIFT 12
+#define SRCODE_READ_XS_MASK (0xff << 12)
+#define PWRDWN_XS_SHIFT 11
+#define PWRDWN_XS_MASK (1 << 11)
+#define DIVIDE_FACTOR_XS_SHIFT 4
+#define DIVIDE_FACTOR_XS_MASK (0x7f << 4)
+#define MULTIPLY_FACTOR_XS_SHIFT 1
+#define MULTIPLY_FACTOR_XS_MASK (0x7 << 1)
+#define SRCODE_OVERRIDE_SEL_XS_SHIFT 0
+#define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0)
+
#ifndef __ASSEMBLY__
+struct srcomp_params {
+ s8 divide_factor;
+ s8 multiply_factor;
+};
+
struct omap_boot_parameters {
char *boot_message;
unsigned int mem_boot_descriptor;
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 201ed6f..b8d841d 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -59,6 +59,7 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
u32 warm_reset(void);
void force_emif_self_refresh(void);
void get_ioregs(const struct ctrl_ioregs **regs);
+void srcomp_enable(void);
/*
* This is used to verify if the configuration header
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 8a886ec..0af0c33 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -153,6 +153,7 @@ struct prcm_regs {
/* cm2.core */
u32 cm_coreaon_bandgap_clkctrl;
+ u32 cm_coreaon_io_srcomp_clkctrl;
u32 cm_l3_1_clkstctrl;
u32 cm_l3_1_dynamicdep;
u32 cm_l3_1_l3_1_clkctrl;
@@ -300,6 +301,7 @@ struct prcm_regs {
u32 cm_wkup_rtc_clkctrl;
u32 cm_wkup_bandgap_clkctrl;
u32 cm_wkupaon_scrm_clkctrl;
+ u32 cm_wkupaon_io_srcomp_clkctrl;
u32 prm_vc_val_bypass;
u32 prm_vc_cfg_i2c_mode;
u32 prm_vc_cfg_i2c_clk;