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| author | Tom Rini <trini@konsulko.com> | 2016-12-12 07:19:28 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-12-12 07:19:28 -0500 |
| commit | b591730c357fd9347c4134ac2883ae039b79915c (patch) | |
| tree | f83d35d58b178dea34fed7dd71352e1aaa4eefb9 /arch/arm/include | |
| parent | fe9822556e051e6c24a3832532166ade00a81a8c (diff) | |
| parent | a20b7a2a53d3ac668d1ed25b06cd6d15ca41f2a9 (diff) | |
| download | u-boot-imx-b591730c357fd9347c4134ac2883ae039b79915c.zip u-boot-imx-b591730c357fd9347c4134ac2883ae039b79915c.tar.gz u-boot-imx-b591730c357fd9347c4134ac2883ae039b79915c.tar.bz2 | |
Merge git://www.denx.de/git/u-boot-marvell
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-armada8k/cache_llc.h | 21 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-armada8k/soc-info.h | 17 |
2 files changed, 38 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-armada8k/cache_llc.h b/arch/arm/include/asm/arch-armada8k/cache_llc.h new file mode 100644 index 0000000..8f97e6d --- /dev/null +++ b/arch/arm/include/asm/arch-armada8k/cache_llc.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2016 Marvell International Ltd. + * + * SPDX-License-Identifier: GPL-2.0 + * https://spdx.org/licenses + */ + +#ifndef _CACHE_LLC_H_ +#define _CACHE_LLC_H_ + +/* Armada-7K/8K last level cache */ + +#define MVEBU_A8K_REGS_BASE_MSB 0xf000 +#define LLC_BASE_ADDR 0x8000 +#define LLC_CACHE_SYNC 0x700 +#define LLC_CACHE_SYNC_COMPLETE 0x730 +#define LLC_FLUSH_BY_WAY 0x7fc +#define LLC_WAY_MASK 0xffffffff +#define LLC_CACHE_SYNC_MASK 0x1 + +#endif /* _CACHE_LLC_H_ */ diff --git a/arch/arm/include/asm/arch-armada8k/soc-info.h b/arch/arm/include/asm/arch-armada8k/soc-info.h new file mode 100644 index 0000000..bae3995 --- /dev/null +++ b/arch/arm/include/asm/arch-armada8k/soc-info.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2016 Marvell International Ltd. + * + * SPDX-License-Identifier: GPL-2.0 + * https://spdx.org/licenses + */ + +#ifndef _SOC_INFO_H_ +#define _SOC_INFO_H_ + +/* Pin Ctrl driver definitions */ +#define BITS_PER_PIN 4 +#define PIN_FUNC_MASK ((1 << BITS_PER_PIN) - 1) +#define PIN_REG_SHIFT 3 +#define PIN_FIELD_MASK ((1 << PIN_REG_SHIFT) - 1) + +#endif /* _SOC_INFO_H_ */ |