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authorPraveen Rao <prao@ti.com>2015-03-09 17:12:06 -0500
committerTom Rini <trini@konsulko.com>2015-03-13 09:29:01 -0400
commit5f603761c3de00423cad405e064cd2fc822feab1 (patch)
treeb4a5ed5a564c806d6fbee7f8f93e87cae55f81d2 /arch/arm/include
parent49ec9490918909c9694b8ee64789f1eed335df1b (diff)
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ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870
This patch enables the workaround for ARM errata 798870 for OMAP5 / DRA7 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock." An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced here as well. Signed-off-by: Praveen Rao <prao@ti.com> Signed-off-by: Angela Stegmaier <angelabaker@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/arch-omap5/sys_proto.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 1038303..ea84665 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -66,4 +66,7 @@ static inline u32 usec_to_32k(u32 usec)
{
return div_round_up(32768 * usec, 1000000);
}
+
+#define OMAP5_SERVICE_L2ACTLR_SET 0x104
+
#endif