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authorTom Rini <trini@konsulko.com>2016-02-23 15:35:47 -0500
committerTom Rini <trini@konsulko.com>2016-02-23 15:35:47 -0500
commit52dd704bf8eda7ca039cdb398ec0b6895c3ef939 (patch)
tree16218aaacdd67330bfc1a6863a9f9dbcf73170fe /arch/arm/include
parentb625fab7069cab52fd8e0c3dbb25e0d04d020173 (diff)
parentdc44fd8ae4be0a88123a90ae2b3acdec45290ecf (diff)
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Merge branch 'master' of http://git.denx.de/u-boot-sunxi
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/arch-sunxi/clock_sun6i.h22
-rw-r--r--arch/arm/include/asm/arch-sunxi/cpu_sun4i.h8
2 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 554d858..9de7754 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -229,8 +229,18 @@ struct sunxi_ccm_reg {
/* ahb_gate0 offsets */
#define AHB_GATE_OFFSET_USB_OHCI1 30
#define AHB_GATE_OFFSET_USB_OHCI0 29
+#ifdef CONFIG_MACH_SUN8I_H3
+/*
+ * These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call
+ * them 0 - 2 like they were called on older SoCs.
+ */
+#define AHB_GATE_OFFSET_USB_EHCI2 27
+#define AHB_GATE_OFFSET_USB_EHCI1 26
+#define AHB_GATE_OFFSET_USB_EHCI0 25
+#else
#define AHB_GATE_OFFSET_USB_EHCI1 27
#define AHB_GATE_OFFSET_USB_EHCI0 26
+#endif
#define AHB_GATE_OFFSET_USB0 24
#define AHB_GATE_OFFSET_MCTL 14
#define AHB_GATE_OFFSET_GMAC 17
@@ -263,13 +273,25 @@ struct sunxi_ccm_reg {
#define CCM_USB_CTRL_PHY0_RST (0x1 << 0)
#define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
#define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
+#define CCM_USB_CTRL_PHY3_RST (0x1 << 3)
/* There is no global phy clk gate on sun6i, define as 0 */
#define CCM_USB_CTRL_PHYGATE 0
#define CCM_USB_CTRL_PHY0_CLK (0x1 << 8)
#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9)
#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
+#define CCM_USB_CTRL_PHY3_CLK (0x1 << 11)
+#ifdef CONFIG_MACH_SUN8I_H3
+/*
+ * These are OHCI1 - OHCI3 in the datasheet (OHCI0 is for the OTG) we call
+ * them 0 - 2 like they were called on older SoCs.
+ */
+#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 17)
+#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 18)
+#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 19)
+#else
#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)
+#endif
#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0
#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index 0cdefdc..b6e11eb 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -52,10 +52,18 @@
#define SUNXI_USB2_BASE 0x01c1c000
#endif
#ifdef CONFIG_SUNXI_GEN_SUN6I
+#ifdef CONFIG_MACH_SUN8I_H3
+#define SUNXI_USBPHY_BASE 0x01c19000
+#define SUNXI_USB0_BASE 0x01c1a000
+#define SUNXI_USB1_BASE 0x01c1b000
+#define SUNXI_USB2_BASE 0x01c1c000
+#define SUNXI_USB3_BASE 0x01c1d000
+#else
#define SUNXI_USB0_BASE 0x01c19000
#define SUNXI_USB1_BASE 0x01c1a000
#define SUNXI_USB2_BASE 0x01c1b000
#endif
+#endif
#define SUNXI_CSI1_BASE 0x01c1d000
#define SUNXI_TZASC_BASE 0x01c1e000
#define SUNXI_SPI3_BASE 0x01c1f000